Xilinx Virtex-6 FPGA, Руководство пользователя

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Virtex-6 FPGA System Monitor www.xilinx.com 49
UG370 (v1.1) June 14, 2010
Application Guidelines
analog power supply and ground reference are also routed into the center of the BGA
using traces. No power planes are required to supply a ground reference for System
Monitor. The analog supply and ground reference are connected to the external reference
IC as shown in
Figure 24, page 46 . In the PCB implementation shown in Figure 28 , the
supply and ground traces are routed on either side of the reference traces on the same
signal layer and act as guards between the reference traces and any potential aggressors
(e.g., clocks and switching I/Os). It is not a requirement that the supply and ground traces
are routed on the same signal layer as shown, but they should be routed on an adjacent
layer. The V
REFN
and AV
SS
traces should be connected at (or close to) the ground pin of the
reference IC. The ferrite bead that connects the analog ground trace to system ground
should also be placed close to the reference IC. Also shown in
Figure 28 is the routing (from
the top) of the dedicated analog input pair (V
P
and V
N
). These inputs are also routed as a
differential pair.
The external reference IC should be placed as close as possible to the FPGA to reduce the
opportunities for coupled noise and to minimize any impedances in the reference traces.
The staggered via field also allows the 10 nF decoupling on V
REFP
and AV
DD
to be placed
in the center of the array close to the package balls. V
REFP
should be decoupled to V
REFN
and AV
DD
to AV
SS
near the package balls.
When using the on-chip reference, the layout of the PCB is greatly simplified. The V
REFP
and V
REFN
pins should be shorted to AGND locally at the package balls - see Figure 24,
page 46 . The ferrite beads used to separate AGND and digital GND should be placed close
to the System Monitor balls in the center of the array along with a 10 nF decoupling
capacitor for AV
DD
.
Figure 27 and Figure 28 are only intended to guide a PC board implementation. If it is
feasible to create an analog reference plane, then there is no issue with doing this.
However, the reference inputs should still be routed as differential pairs as shown.
Example Instantiation of SYSMON
The following sample design is intended to illustrate a basic instantiation of the Virtex-6
FPGA System Monitor in a design (refer to
System Monitor Primitive, page 8 for details on
the System Monitor I/O and attributes). Figure 29 illustrates a block diagram of the sample
design. In this design, SYSMON is set up to monitor the V
CCAUX
supply and generate an
alarm on ALM[2], if the monitored supply moves outside the specified limits. The
measured value of V
CCAUX
can be checked at any time on the DO bus. The design requires
an external clock to be provided. This design uses a 50 MHz external clock.
Note:
Because an internal clock divider is provided, a clock in the range 2 MHz to 200 MHz can be
used as a clock source.
The BUSY signal is also brought out so the ADC conversion rate is easily monitored. The
BUSY signal is also used to clock the DO data into a logic analyzer or other data acquisition
system for inspection. By varying the V
CCAUX
supply on the board, the alarm can be
triggered or the varying supply voltage can be monitored on the DO bus.
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