Xilinx LogiCORE IP Video In to AXI4-Stream v1.0, Руководство по эксплуатации продукта

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Video In to AXI4-Stream www.xilinx.com 9
PG043 April 24, 2012 Product Specification
Resource Utilization
Throughput
The average data rates of active pixels on the AXI4-Stream interface matches the average
rate of active pixels in on the Video bus. However, the clock rates of the input and output
need not match. Furthermore, since the AXI4-Stream bus does not carry blank pixels, the
clock rate can be lower than the video clock rate and still have sufficient bandwidth to meet
the average rate requirement. Additional FIFO depth is required in order to smooth the
mismatch in instantaneous rates. Both the input video pixel clock (Fvclk) and the rate of the
AXI4-Stream Clock (Faclk) is limited by the overall Fmax.
If Faclk is equal to or greater than Fvclk, only the minimum buffer size (32 locations) is
required. This assumes that the cores connected downstream of the Video In to
AXI4-Stream core can sink data at the full video rate. e.g. The downstream core can accept
data in a virtually continuous stream with gaps occurring only following EOL, and each line
consecutively with line gaps only preceding SOF. In this scenario, the FIFO will go empty
after the EOL on each line.
If Faclk is less than Fvclk, additional buffering is required. The FIFO must be large enough to
handle the differential in the rate that pixels are coming in on the video clock, and the
slower rate that they can go out on the AXI4-Stream bus using aclk. For aclk frequencies
above the line average but below that of vclk, the input FIFO depth must be:
FIFO depth min =32 + Active Pixels * Fvclk/Faclk
If the downstream processing core accepts data at a lower rate than the
aclk
, additional
buffering is required in an amount sufficient to prevent the FIFO from overflowing during
the course of a frame.
Resource Utilization
The information presented in Table 2-1 through Table 2-6 is a guide to the resource
utilization and maximum clock frequency of the Video In to AXI4-Stream core for Virtex-7,
Kintex-7, Artix-7, Zynq-7000, Virtex-6, and Spartan-6 FPGA families. The design was tested
using ISE
®
v14.1 tools with default tool options for characterization data.
Note:
Data width in the following tables refers to the aggregate data width of all the video
components into and out of the core. For example, RGB data with 8-bits per component has a data
width of 24.
Table 2-1: Spartan-6
Data Width FIFO Depth LUTs FFs RAM 16/8 Fmax (MHz)
8 32 83 104 0/0 223
24 1024 147 161 1/1 209
64 8192 204 264 33/0 129