Video In to AXI4-Stream
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PG043 April 24, 2012
Product Specification
Chapter 2
Product Specification
Standards Compliance
The Video In to AXI4-Stream core is compliant with the AXI4-Stream Video Protocol and
AXI4-Lite interconnect standards. Refer to the
Video IP: AXI Feature Adoption
section of the
for additional information.
Performance
The following sections detail the performance characteristics of the Video In to
AXI4-Stream core.
Maximum Frequencies
This section contains typical clock frequencies for the target devices. The maximum
achievable clock frequency can vary. The maximum achievable clock frequency and all
resource counts can be affected by other tool options, additional logic in the FPGA device,
using a different version of Xilinx tools and other factors. Refer to in
through
for device-specific information.
Latency
When the downstream processing block on the AXI4-Stream bus can take data at the pixel
rate or faster, the typical latency through the Video In to AXI4-Stream core is 6 cycles of
vid_ 3 cycles of aclk.
If the downstream block takes pixels at a slower rate, the FIFO will be used to even out the
mismatch in the input and output rates over the course of lines and frames. This storage of
pixels in the FIFO will add to the latency and will vary according to the data flow in and out
of the core.
