Video In to AXI4-Stream
12
PG043 April 24, 2012
Product Specification
Core Interfaces and Register Space
Video Timing Pass-Through Outputs
Video Input Interface
The Video In to AXI4-Stream core receives standard video data using the Video Input
interface and transmits data using AXI4-Stream interfaces that implement a video protocol
as defined in the
AXI Reference Guide (UG761)
, Video IP: AXI Feature Adoption section.
empty
Out
1
Active HIGH FIFO empty flag.
1 = FIFO read was attempted when FIFO was empty.
Due to EOL flushing, this flag will be asserted at the end of every
line during normal operation.
axis_enable
In
1
Enable the AXI4-Stream bus.
1 = Enable AXI4-Stream bus to operate.
0 = Inhibit AXI4-Stream operation by forcing m_axis_video_tdata
LOW.
Table 2-8:
Port Name I/O Width Description
Signal Name
Direction Width
Description
vtd_vsync
Out
1
Vertical synch video timing signal.
vtd_hsync
Out
1
Horizontal synch video timing signal.
vtd_vblank
Out
1
Vertical blank video timing signal.
vtd_hblank
Out
1
Horizontal blank video timing signal.
vtd_active_video
Out
1
Active video flag.
1 = active video, 0 = blanked video
Table 2-9:
Port Name I/O Width Description
Signal Name
Direction
Width
Description
vid_in_clk
In 1
Video input clock
video_de
In
1
Video data enable.
1 = active video, 0 = blanked video
vid_vsync
In
1
Vertical synch video timing signal. Active High
vid_hsync
In
1
Horizontal synch video timing signal. Active High
vid_vblank
In
1
Vertical blank video timing signal. Active High
vid_hblank
In
1
Horizontal blank video timing signal. Active High
video_data
In
8-64
Parallel video input data.
Table 2-7:
Port Name I/O Width Description
Signal Name
Direction Width
Description
