Xilinx LogiCORE IP Video In to AXI4-Stream v1.0, Руководство по эксплуатации продукта

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Video In to AXI4-Stream www.xilinx.com 27
PG043 April 24, 2012
Chapter 5
Constraining the Core
Required Constraints
The only constraints required are clock frequency constraints for the video clock,
video_in_clk
, and the AXI4-Stream clock,
aclk
. Paths between the two clock domains
should be constrained as false paths, which should be ignored during timing analysis.
For example, the following UCF code could be used to constrain the video clock and the
AXI4-Stream Clock for 150MHz operation:
NET vid_in_clk TNM_NET = vid_in_clk;
TIMESPEC TS_vid_in_clk = PERIOD vid_in_clk 150 MHz HIGH 50%;
NET aclk TNM_NET = aclk;
TIMESPEC TS_aclk = PERIOD aclk 150 MHz HIGH 50%;
TIMESPEC TS_vid_in_clk_to_aclk = FROM vid_in_clk TO aclk TIG;
TIMESPEC TS_aclk_to_vid_in_clk = FROM aclk TO vid_in_clk TIG;
Device, Package, and Speed Grade Selections
There are no device, package, or speed grade requirements for this core. This core has not
been characterized for use in low power devices.
Clock Frequencies
The pixel clock frequency is the required frequency for this core. See Maximum Frequencies
in Chapter 2 .
Clock Management
There are two clock domains for the Video In to AXI4-Stream core. The clock crossing
boundary is handled by the FIFO, and a handshaking system for passing pointers between
domains.