Video In to AXI4-Stream
6
PG043 April 24, 2012
Feature Summary
A Video In to AXI4-Stream core with a video timing generator block diagram is shown in
The core is designed to be used in parallel with the detector functionality of the Video
Timing Controller (VTC). The video timing detector detects the line standard of the
incoming video, and makes the detected timing values, such as the number of active pixels
per line and the number of active lines available to video processing cores downstream of
the Video In to AXI4-Stream core via an AXI4-Lite interface. It is recommended to connect
the “locked” status output of video timing detector to the
axis_enable
input of the Video
In to AXI4-Stream core in order to inhibit the AXI4-Stream bus when the video input is
missing or unstable.
Feature Summary
The Video In to AXI4-Stream core converts a video input, consisting of parallel video data,
video syncs, blanks and data enable, to an AXI4-Stream master bus that follows the
AXI4-Stream Video protocol. The core provides a pass thru of all timing signals for the Xilinx
video timing controller, although the signals for the Video timing Controller are not
required to pass through the Video In to AXI4 Stream core.
The core handles the asynchronous clock boundary crossing between the video clock
domain and the AXI4-Stream clock domain. The data width is selectable from 8 to 64 bits,
X-Ref Target - Figure 1-1
Figure 1-1:
Block Diagram of Video In to AXI4-Stream Core and Usage with the Video Timing Controller
