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Video In to AXI4-Stream

www.xilinx.com

PG043 April 24, 2012

Module Descriptions

The Read Logic controls the

tvalid

handshaking signal based on the level and flags from

the FIFO, and the tready signal returned from the downstream module. Whenever data is

available in the FIFO,

tvalid

is asserted. When

tready

is returned active, the FIFO is read

and the new pixel is again denoted by the

tvalid

being active. Thus, the

tvalid

asserted except when there is no valid data available from the FIFO. The FIFO will only begin

filling if the downstream core cannot accept data as fast as it is coming in from the video

bus. This will happen, for example, if the AXI4-Stream clock,

aclk

, is slower than the video

clock. In this case, during the active portion of each line, pixels will be coming into the FIFO

faster than they can be sent out on the AXI4-Stream bus. Thus the FIFO will begin to fill.

Usually the FIFO will empty at the end of the active line when the downstream core is still

taking pixels, but the incoming video data is in the horizontal blanking period.

At the end of each line, the EOL must be flushed through from the FIFO to the output

registers. This is done so that the downstream core can access the complete line without

having to wait through the horizontal blanking period for new pixels to push the EOL out.

This flushing requirement presents a challenge since this occurs during horizontal blanking,

meaning that no data is coming into the FIFO. It requires generation of invalid pixels to flush

out the valid pixels. Since no inactive pixels are allowed on the AXI4-Stream bus, these

invalid pixels must be swallowed by the core prior to the output.

Flushing of the EOL is accomplished by reading from the FIFO whenever it is not empty or

when it is empty and the last pixel has the EOF (

tlast

) flag set (assuming AXI4-Stream bus

is not applying backpressure). In other words, read the FIFO until it is empty, and beyond

when the EOL is present. When the FIFO is empty, and the last pixel has been read (the EOL

pixel) the FIFO will mark subsequent pixels as invalid, but the EOL will continue to

propagate to the output. Valid pixels get sent out on the AXI-4 Stream bus, invalid pixels do

not. In this way, invalid pixels are swallowed before they get to the AXI-4 Stream bus.

Содержание LogiCORE IP Video In to AXI4-Stream v1.0

Страница 1: ...Video In to AXI4 Stream v1 0 Product Guide PG043 April 24 2012...

Страница 2: ...ion 9 Core Interfaces and Register Space 10 Chapter 3 Customizing and Generating the Core Graphical User Interface GUI 16 Chapter 4 Designing with the Core General Design Guidelines 18 System Consider...

Страница 3: ...il 24 2012 I O Standard and Placement 28 Chapter 6 Detailed Example Design Appendix A Additional Resources Xilinx Resources 30 Solution Centers 30 References 30 Technical Support 31 Ordering Informati...

Страница 4: ...clock boundary crossing between video clock domain and AXI4 Stream clock domain Selectable FIFO depth from 64 8192 locations Selectable input data width of 8 64 bits LogiCORE IP Video In to AXI4 Strea...

Страница 5: ...sync Hsync Vbank Hblank and DE Any of these sets of signals is sufficient for the operation of the Video In to AXI4 Stream core The particular choice is important to the VTC detector so the generation...

Страница 6: ...to the axis_enable input of the Video In to AXI4 Stream core in order to inhibit the AXI4 Stream bus when the video input is missing or unstable Feature Summary The Video In to AXI4 Stream core conver...

Страница 7: ...parallel clocked video sources DVI HDMI Image Sensors Other clocked parallel video sources Licensing The Video In to AXI4 Stream core is provided at no cost with the Xilinx tools Use of it is covered...

Страница 8: ...k frequency can vary The maximum achievable clock frequency and all resource counts can be affected by other tool options additional logic in the FPGA device using a different version of Xilinx tools...

Страница 9: ...O will go empty after the EOL on each line If Faclk is less than Fvclk additional buffering is required The FIFO must be large enough to handle the differential in the rate that pixels are coming in o...

Страница 10: ...Width FIFO Depth LUTs FFs RAM 36 18 Fmax MHz 8 32 83 104 0 0 337 24 1024 120 161 1 0 309 64 8192 221 262 16 1 309 Table 2 3 Virtex 6 Data Width FIFO Depth LUTs FFs RAM 36 18 Fmax MHz 8 32 79 104 0 0 3...

Страница 11: ...el Signaling Interface 6IDEO N TO 8 3TREAM S AXIS VIDEO TDATA S AXIS VIDEO TVALID S AXIS VIDEO TREADY S AXIS VIDEO TLAST M AXIS VIDEO TDATA M AXIS VIDEO TVALID M AXIS VIDEO TREADY M AXIS VIDEO TLAST M...

Страница 12: ...s_video_tdata LOW Table 2 8 Port Name I O Width Description Signal Name Direction Width Description vtd_vsync Out 1 Vertical synch video timing signal vtd_hsync Out 1 Horizontal synch video timing sig...

Страница 13: ...rising edges on the ACLK pin Internal states are maintained and output signal levels are held until ACLKEN is asserted again When ACLKEN is de asserted core AXI4 Stream inputs are not sampled except A...

Страница 14: ...ve that can immediately accept data qualified by m_axis_video_tvalid should pre assert its m_axis_video_tready signal until data is received Alternatively m_axis_video_tready can be registered and dri...

Страница 15: ...Video In to AXI4 Stream www xilinx com 15 PG043 April 24 2012 Product Specification Core Interfaces and Register Space X Ref Target Figure 2 3 Figure 2 3 Use of EOL and SOF Signals...

Страница 16: ...h the CORE Generator GUI This section provides a quick reference to parameters that can be configured at generation time The GUI displays a representation of the IP symbol on the left side and the par...

Страница 17: ...components 1 4 is multiplied by the component width to determine the width of the video data bus v_data In turn this width is rounded up to the nearest factor of 8 to determine the width of the AXI4...

Страница 18: ...ng signals The set of timing signals used should be those required by the VTC detector See the PG016 Video Timing Controller Product Guide for more details For the Video In to AXI4 Stream core the dat...

Страница 19: ...inimum the aclk frequency must be higher than the average pixel rate Resets There are two external resets provided rst which resets the entire core and aresetn which resets the AXI4 Stream interface B...

Страница 20: ...n Fvclk additional buffering is required The FIFO must store enough pixels to supply pixels continuously throughout the active line Additionally due to phasing requirements the horizontal active perio...

Страница 21: ...ing edge of DE however it additionally requires knowledge of the vertical timing to identify the first line This is done using the logical or OR vsync and vblank The falling edge of either of these in...

Страница 22: ...use case of reads when the FIFO is empty It also has pointer inhibiting logic to prevent pointer crossings on underflow and overflow This asynchronous nature of the FIFO presents challenges for the f...

Страница 23: ...the read logic is simple with binary pointers but impractical with gray code pointers Clock Domain Crossing of Pointers The synchronization and handshaking for pointers is shown in detail in Figure 4...

Страница 24: ...states request and acknowledge The request state is when Req and Ack are not equal and acknowledge is when they are equal This sample and hold method with handshaking delays the capture of the pointe...

Страница 25: ...from the FIFO as invalid The data output however will not change Thus when a read occurs to an empty FIFO the invalid flag read_error is set and the read pointer does not increment In this way the EO...

Страница 26: ...tal blanking period At the end of each line the EOL must be flushed through from the FIFO to the output registers This is done so that the downstream core can access the complete line without having t...

Страница 27: ...TS_vid_in_clk PERIOD vid_in_clk 150 MHz HIGH 50 NET aclk TNM_NET aclk TIMESPEC TS_aclk PERIOD aclk 150 MHz HIGH 50 TIMESPEC TS_vid_in_clk_to_aclk FROM vid_in_clk TO aclk TIG TIMESPEC TS_aclk_to_vid_i...

Страница 28: ...e no specific Clock placement requirements for this core Banking There are no specific Banking rules for this core Transceiver Placement There are no Transceiver Placement requirements for this core I...

Страница 29: ...Video In to AXI4 Stream www xilinx com 29 PG043 April 24 2012 Chapter 6 Detailed Example Design No example design is available at the time for the LogiCORE IP Video In to AXI4 Stream v1 0 core...

Страница 30: ...s glossary pdf For a comprehensive listing of Video and Imaging application notes white papers reference designs and related IP cores see the Video and Imaging Resources page at http www xilinx com es...

Страница 31: ...Answer Record that contains the Release Notes and Known Issues list for the core being used The following information is listed for each version of the core New Features Resolved Issues Known Issues O...

Страница 32: ...ult of any action brought by a third party even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same Xilinx assumes no obligation to correct any...

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