Programmable Field Bus Controller 750-833
•
67
Process Image
WAGO-I/O-SYSTEM 750
Bus System
3.4.6 Addressing
3.4.6.1
I/O Module Data
The CPU has direct access to the bus terminal data through absolute
addresses. Addressing is organized word-by-word and begins with the address
0 both with inputs and outputs. The corresponding addresses for bits, bytes
and double words (dword) are derived from the word addresses.
Data Size
Addresses up to SW 02
Bit 0.0
...
0.7
0.8
...
0.15
1.0
...
1.7
1.8
...
1.15
... 62.0
...
62.7
62.8
...
62.15
63.0
...
63.7
63.8
...
63.15
Byte 0
1
2
3
...
124
125
126
127
Word 0 1
...
62 63
Dword 0
...
31
Data Size
Addresses from SW 03
Bit 0.0
...
0.7
0.8
...
0.15
1.0
...
1.7
1.8
...
1.15
... 120.0
...
120.7
120.8
...
120.15
121.0
...
121.7
121.8
...
121.15
Byte 0
1
2
3
...
240
241
242
243
Word 0 1
...
120 121
Dword 0
...
60
The structure of the process image is described in chapter 3.4., “Process
Image” is done in this structure.
Input data
%IW0
|
%IW
n
word oriented data
%I
n+1
|
%I
n+m
bit oriented data
Output data
%QW0
|
%QW
n
word oriented data
%Q
n+1
|
%Q
n+m
bit oriented data
