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EMX-75XX Index
35
FPGA
GND_S
DATAx.y
DIO conn
PXIe conn
R1A
330
Ω
R1B
499
Ω
R1C
100 k
Ω
3.7 V
LV Emulation
5 V
TTL Emulation
VCLAMP
Channel
Control
Over-Current
Detect
User
Voltage
ESD
Int. Voltage
(3.3, 5, 12,
24V)
GND_S
R
USER
Voltage Output
Mode
Internal Supply Pull-Up (
R
X
)
Open Circuit V
0
Normal
24 V
100
kΩ (
R
3
)
~24 V
Normal
12 V
100
kΩ (
R
3
)
~12 V
Normal
5 V
100
kΩ (
R
3
)
~5 V
Normal
3.3 V
100
kΩ (
R
3
)
~3.3 V
TTL Emulation
5 V*
499
Ω (
R
2
)
~
4.64 V
LV Emulation
3.7 V*
330
Ω (
R
1
)
~
3.34 V
*For TTL and LV modes, there is approximately a 0.35 V drop due to the Schottky diode, resulting in an actual
internal supply voltage of 4.65 V and 3.35V, respectively.
Mode
External Supply
Load
V
O-USER
Normal
V
CLAMP
R
USER
(
)
+
Ω
USER
USER
CLAMP
R
k
R
V
100
F
IGURE
2-18:
V
OLTAGE
O
UTPUT
B
LOCK
D
IAGRAM
Connector Pin/Signal Assignment
The connector pins and their signal assignments are shown below Table 2-8. For mating connector
