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EMX-75XX Index
15
FPGA
GND_S
Input Detect with
Hysteresis
DATAx.y
DIO conn
PXIe conn
R1A
330
Ω
R1B
499
Ω
R1C
100 k
Ω
3.7 V
LV Emulation
5 V
TTL Emulation
VCLAMP
Channel
Control
Over-Current
Detect
R
INPUT
201 k
User
Voltage
ESD
Int. Voltage
(3.3, 5, 12,
24V)
R
USER
GND_S
GND_S
Voltage Output
Mode
Internal Supply Pull-Up (
R
X
)
Open Circuit V
0
Normal
24 V
100
kΩ (
R
3
)
~
15.84 V
Normal
12 V
100
kΩ (
R
3
)
~
7.92 V
Normal
5 V
100
kΩ (
R
3
)
~
3.3 V
Normal
3.3 V
100
kΩ (
R
3
)
~
2.47 V
TTL Emulation
5 V*
499
Ω (
R
2
)
~
4.64 V
LV Emulation
3.7 V*
330
Ω (
R
1
)
~
3.34 V
*For TTL and LV modes, there is approximately a 0.35 V drop due to the Schottky diode, resulting in an actual
internal supply voltage of 4.65 V and 3.35V, respectively.
Mode
External Supply
Load
V
O-USER
Normal
V
CLAMP
R
USER
(
)
+
Ω
INPUT
USER
INPUT
USER
CLAMP
R
R
k
R
R
V
||
100
||
F
IGURE
2-2:
V
OLTAGE
O
UTPUT
B
LOCK
D
IAGRAM
Connector Pin/Signal Assignment
The connector pins and their signal assignments are shown below Table 2-1. For mating connector
and accessory information, please see the
Pin
Signal
Pin
Signal
Pin
Signal
Pin
Signal
Pin
Signal
A1
GND_S
B1
GND_C
C1
GND_S
D1
EXT_GATE_AC
Q
E1
EXT_GATE_GE
N
A2
GND_S
B2
GND_S
C2
GND_S
D2
EXT_CLK
E2
GND_S
A3
DATA1.
B3
GND_S
C3
DATA1.
D3
GND_S
E3
DATA1.5