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EMX-75XX Index
21
The falling edge is much sharper with a maximum fall time of 300 ns approximately. When the
port is set as input, the data lines are pulled up using 100
kΩ resistor. Pleas
e refer to electrical
characteristics for output voltage levels with different load resistance.
The load resistor and pull-up resistor form a voltage divider of V
CLAMP
and determine output
voltage, thus output voltage decreases with decreasing load resistance. The minimum load
resistance that can be connected on channels is 500
Ω for LV emulation, 750
Ω for TTL emulation
and 150
kΩ otherwise.
The data lines have a current sinking capacity of 300 mA. If the current through MOSFET
increases above limited value, the over current protection circuit turns off all FETs in the
concerned port. The over current condition must last for greater than 12.8 µs before over current
protection circuit is activated. This is done to prevent false over current events due to transients. It
takes approximately 20 µs from first occurrence of the over current event before the FETs are
truned off. The over current circuit will activate with 340 mA hold current and 475 mA trip
current, where hold current is the maximum current circuit will allow without tripping and trip
current is the minimum current required to trip the circuit. The absolute maximum limit on sinking
current is 500 mA. Staying within these limits is user’s responsibility. Over current readings from
ports will be latched and can be read by user. When they reset over current condition then port will
be enabled and data last written to port will be applied on channels.
Input Section
The input section converts the high or low voltage reading on the data channels to 1 or 0 that can
be read by the user. The port’s V
CLAMP
voltage is used as a reference for threshold detection. If
voltage on data line is greater than 40% (range spreads to 37% to 42% across different voltage
levels) of port’s V
CLAMP
voltage, 1 is read and if voltage on data line is less than 13% (10% to16%
range) of port’s V
CLAMP
voltage, 0 is read. Hysteresis loop is implemented on input comparison
meaning that on rising voltage, level has to cross higher threshold (VIH) to record a 1 and on
falling voltage, level has to cross lower threshold (VIL) to record a 0. In between VIH and VIL the
digital state of data channel reading stays the same. Please refer to the recommended operating
conditions for input threshold values.
The input section also has a fly-back protection diode. The port’s reference voltage VCLAMP is
routed to the cathode of a fly-back protection diode, whose anode is then connected to the
associated port’s data line. Every data line has a diode installed to suppress transients in case of
voltage overshooting. The current through diode must be limited as indicated in absolute
maximum ratings.