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PKP

VS1000 P

ROGRAMMER

’

S

G

UIDE

VSMPG

•

Enable registers, which contain enable/disable bits for each interrupt source. Bit
pairs configure the interrupt priority and disable.

•

Origin registers, which contain the source flags for each interrupt. A request from
an interrupt source sets the corresponding bit. A bit is automatically reset when a
request for the source is generated.

•

Enable counter register, which contains the value of the General Interrupt Enable
counter, and two registers for increasing and decreasing the value.

15.1.1

Enable INT_ENABLE[L/H][0/1]

Interrupt enable registers selectively masks interrupt sources. Enable registers 0 contain
sources 0..15 and enable registers 1 contain sources 16..31. Each source has two
enable bits: one in the enable low and one in the enable high register. If both bits are
zero, the corresponding interrupt source is not enabled, otherwise the bits select the
interrupt priority.

High

Low

Priority

0

0

Source disabled

0

1

Priority 1

1

0

Priority 2

1

1

Priority 3

Priorities only matter when the interrupt controller decides which interrupt to generate
for the core next. This happens whenever two interrupt sources request interrupts at the
same time, or when interrupts become enabled after an interrupt handler routine or part
of code where the interrupts have been disabled.

15.1.2

Origin INT_ORIGIN[0/1]

If an interrupt source requests an interrupt, the corresponding bit in the interrupt ori-
gin register (ORIGIN0 or ORIGIN1) will be set to ’1’. If an interrupt source is enabled
(using ENABLE registers), the interrupt controller generates an interrupt request signal
for VSDSP with the corresponding vector value. The bit in the origin registers is reset
automatically after the interrupt is requested.

If the source is not enabled, the processor can read the origin register state and perform
any necessary actions without using interrupt generation, i.e. polling of the interrupt
sources is also possible. The bits in the interrupt origin registers can be cleared by
writing ’1’ to them.

A read from the interrupt origin register returns the register state.

A write to the interrupt origin register clears bits in the interrupt origin register. All ’1’-
bits in the written value cause the corresponding bits in the interrupt origin register to
be cleared. All zero-bits cause the corresponding bits in the interrupt origin register to

Rev. 0.20

2011-10-04

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Содержание VS1000

Страница 1: ...akes and typ ing errors Please contact VLSI if you suspect an error Revision History Rev Date Author Description 0 1 2007 03 23 PKP Preliminary version 0 11 2007 04 16 PKP Minor adjustments 0 12 2007 06 28 PKP Additions for version 1 33 of developer tools 0 14 2007 06 28 PKP VS1000B minor update 0 15 2008 06 30 POj vskit1 34 lib and include merged 0 16 2009 07 06 POj USB register map fixed 0 20 20...

Страница 2: ...VS1000A It is mainly com patible with VS1000A but code needs to be recompiled for VS1000B This guide was originally written for VS1000A so it may not show all of the extra features in VS1000B VS1000C is another production test version of VS1000B with identical ROM VS1000D VS1000D includes bug fixes but is fully backwards compatible with VS1000C All soft ware works without recompilation so VS1000D ...

Страница 3: ... 7 1 3 Loading 19 7 1 4 Note 20 7 1 5 Input and Output 20 7 2 Making the LEDs blink 22 7 3 Adjusting the Player User Interface 23 7 4 Hooking custom storage controller 25 7 4 1 ReadDiskSector is for reading only 26 7 5 Setting your own USB descriptors 29 7 5 1 Descriptor data format 29 8 Booting from SPI EEPROM 32 8 0 2 Using a VS1000 Developer Board as an eeprommer 32 9 Booting from NAND FLASH 36...

Страница 4: ... 49 14 2 2 Output Data GPIOx_ODATA 49 14 2 3 Input Data GPIOx_IDATA 50 14 2 4 Falling Edge Interrupt Enable GPIOx_INT_FALL 50 14 2 5 Rising Edge Interrupt Enable GPIOx_INT_RISE 50 14 2 6 Interrupt Pending Source GPIOx_INT_PEND 50 14 2 7 Data Set Mask GPIOx_SET_MASK 50 14 2 8 Data Clear Mask GPIOx_CLEAR_MASK 51 14 2 9 Bit Engine Config GPIOx_BIT_CONF 51 14 2 10Bit Engine 0 Read Write GPIOx_BIT_ENG0...

Страница 5: ...parity registers 68 17 3 3 Data register 69 17 3 4 Interface control towards physical pins 69 17 3 5 Interface control towards DSP 70 17 3 6 ECC counter register 70 17 4 Timing 71 17 5 VS1000 ROM code usage 75 17 5 1 Nand Flash access methodology 75 18 Timers v1 0 2002 04 23 76 18 1 General 76 18 2 Registers 76 18 2 1 Configuration TIMER_CONFIG 76 18 2 2 Configuration TIMER_ENABLE 77 18 2 3 Timer ...

Страница 6: ...2 6 USB_EP_SENDn EPnIN Transmittable Packet Info 0xC088 0xC08B 84 20 2 7 USB_EP_STn Endpoint flags EPnIN and EP0nUT 0xC090 0xC093 84 20 3 Receiving Packets from PC EP0OUT EP1OUT EP3OUT 85 20 3 1 Reception 85 20 3 2 Sending Packet to PC EP0IN EP1IN EP3IN 86 20 3 3 How to know that the PC is expecting data 86 20 3 4 Stalling 86 20 4 VS1000 ROM code usage 87 20 4 1 Augmenting the ROM functionality 88...

Страница 7: ...reo DAC and an earphone amplifier and a common voltage buffer Reference Regulator Regulator Regulator Common Voltage Driver Voltage Monitor Stereo Earphone Driver Stereo DAC AVDD1 AVDD2 AVDD3 Serial Data Control Interface UART Clock NAND Flash Interface General IO 1 6V USB X RAM X ROM Y RAM Y ROM I RAM I ROM VSDSP4 processor USBP USPN XCS GPIO1 0 SCLK GPIO1 1 SI GPIO1 2 SO GPIO1 3 RX GPIO1 5 TX GP...

Страница 8: ...U control registers decode logic Peripheral interface PLL clock generator Peripheral devices Interrupt arbitrator Boot loader Bus switch Figure 2 VS_DSP General Architecture Most of the features of the VS_DSP processor can be accessed by using standard C language without any specific VS_DSP knowledge But if you need to develop really powerful DSP algorithms use the 40 bit datapath control the pipe...

Страница 9: ...bytes X 412 bytes Y total 10524 bytes 9216 words 18432 bytes ing vorbis and disk cache when USB is connected Vorbis heap when play Total stack space 1024 bytes X 1024 bytes Y total 2048 bytes for user and system Total RAM space 26624 bytes X 32768 bytes Y 8192 bytes I total 67584 bytes stack space and function local variables Figure 3 VS1000B RAM layout While playing Ogg Vorbis audio the memory ar...

Страница 10: ...te buffer and ECC calculation 2 32 bit timers with shared master clock divider Interrupt controller 11 interrupt sources 3 programmable linear regulators for generating analog I O and core voltages Internal oscillator for external crystal can also use external oscillator Integrated Clock Generator with PLL and clock multiplier and low speed modes Watchdog timer The VS1000 has 76 KiB of program ROM...

Страница 11: ...IMER_CONFIG Timer 0 and 1 Configuration 0xC031 TIMER_ENABLE Timer 0 and 1 Enable Disable 0xC034 TIMER_T0L Low 16 bits of Timer 0 reload value 0xC035 TIMER_T0H High 16 bits of Timer 0 reload value 0xC036 TIMER_T0CNTL Low 16 bits of Timer 0 current value 0xC037 TIMER_T0CNTH High 16 bits of Timer 0 current value 0xC038 TIMER_T1L Low 16 bits of Timer 1 reload value 0xC039 TIMER_T1H High 16 bits of Tim...

Страница 12: ...68 SPI0_CONFIG Serial Peripheral Interface Configuration 0xC069 SPI0_CLKCONFIG SPI Clock Configuration 0xC06A SPI0_STATUS SPI Status 0xC06B SPI0_DATA SPI Data read write register 0xC06C SPI0_FSYNC Frame Sync output bit image 0xC070 INT_ENABLEL Low Priority Interrupt Enable 0xC072 INT_ENABLEH High Priority Interrupt Enable 0xC074 INT_ORIGIN Interrupt Request Status 0xC076 INT_VECTOR Last generated ...

Страница 13: ...5 10 Nand flash IO5 General purpose IO Port 0 bit 5 GPIO0 6 NFDIO6 11 Nand flash IO6 General purpose IO Port 0 bit 6 GPIO0 7 NFDIO7 12 Nand flash IO7 General purpose IO Port 0 bit 7 GPIO0 8 NFRDY 13 Nand flash READY General purpose IO Port 0 bit 8 GPIO0 9 NFRD 14 Nand flash RD General purpose IO Port 0 bit 9 GPIO0 10 NFCE 15 Nand flash CE General purpose IO Port 0 bit 10 GPIO0 11 NFWR 20 Nand flas...

Страница 14: ...ate Set sample rate 0x001a PowerOff RealPowerOff Close and shutdown 0x001c PlayCurrentFile RealPlayCurrentFile Start playing file 0x001e USBHandler RealUSBHandler USB Task VS1000 Handler Vectors Interrupt Controller Address Vector Name Default Handler Remark 0x0020 DAC Interrupt dac_int Update sample 0x0021 SPI Interrupt _int Default Null Handler 0x0022 USB Interrupt _int Default Null Handler 0x00...

Страница 15: ... UnsupportedFile DefUnsupportedFile Unknown format Additional VS1000B Handler Vectors Services 0x0036 KeyEventHandler RealKeyEventHandler Perform actions for key events 0x0038 MassStorage RealMassStorage USB Mass Storage code 0x003a USBSuspend RealUSBSuspend Code for low power mode used by USB and low power pause 0x003c InitUSBDescriptors RealInitUSBDescriptors Hook to initialize USB descriptors 0...

Страница 16: ...e and contains example projects for VS1000 The various tools can be downloaded from VLSI Solution s Web Pages www vlsi fi See under Support Software 6 1 vcc The VLSI C Compiler Creates a COFF object file from C language source file Example vcc P130 O fsmall code I lib o program o program c 6 2 vslink The linker Creates a binary program file from multiple COFF object files Example vslink k m mem_us...

Страница 17: ...compatible boot record file from a binary program file Example coff2nandboot t 3 b 8 s 19 w 50 x 0x50 led bin nand rec 6 6 makenandimage required for VS1000A only Creates a prommable binary nand flash image from a nand flash compatible boot record file Example makenandimage nand rec NANDFLSH IMG Rev 0 20 2011 10 04 Page 17 90 ...

Страница 18: ...compiled and linked Then the RS 232 ROM monitor interface vs3emu is used to load and execute the code The contents of the file hello c is hello c A Hello World example include stdio h main is the program entry point It is entered via a vector which is statically linked to address 0x0050 in module c o void main void puts Hello World 7 1 1 Compiling The hello c file is compiled using vcc with a comm...

Страница 19: ...oad the code using an RS 232 COM port emulator interface which connects to the RX and TX pins of VS1000 1 Note that a program booting from SPI and NAND FLASH may interfere with the loaded program You can disable SPI boot and erase the boot program part from NAND FLASH to make certain Leave the NAND FLASH ident so the NAND FLASH can be used by the ROM firmware and your program The PC side interface...

Страница 20: ...0 s 115200 l hello bin e cmd The emulator can be exited by pressing Ctrl C 7 1 4 Note If your board has boot code in the Nand Flash the Nand Flash boot code runs after main exits 7 1 5 Input and Output This example uses the vs3emu interface to handle C standard I O stdin stdout With it it s possible to write messages to the user and read input from the PC keyboard Also it s possible to open read a...

Страница 21: ... tmp 4 tmp 5 0 fputs tmp stdout Also note that if you use puts or any file input output in your code a connection with vs3emu is required You should carefully remove any such code before porting the code to be loaded via another method than vs3emu such as a boot flash or eeprom This could be done by surrounding the I O code with ifdef DEBUG and endif pre proces sor directives Rev 0 20 2011 10 04 P...

Страница 22: ...DATA 0x04 GPIO1 2 LQFP pin 24 1 BusyWaitHundreths 50 PERIP GPIO1_ODATA 0x08 GPIO1 3 LQFP pin 25 1 BusyWaitHundreths 50 The SPI port pins and UART port pins are controlled by the same I O controller I O controller 1 When disabling peripheral control of the SPI pins the UART pins RX TX must remain under peripheral control Otherwise the connection with vs3emu is lost For reference here are the GPIO1 ...

Страница 23: ...n 0 ke_null Do nothing 1 ke_previous Play Previous song 2 ke_next Play Next song 3 ke_rewind Rewind 4 ke_forward Fast Forward 5 ke_volumeUp Volume Up 6 ke_volumeDown Volume Down 7 ke_earSpeaker Switch EarSpeaker processing 4 settings 8 ke_earSpeakerToggle Toggle EarSpeaker processing 2 settings 9 ke_randomToggle Random Play on off 10 ke_randomToggleNewSong Play random song 11 ke_pauseToggle Pause ...

Страница 24: ...us KEY_C ke_previous Key C Previous song KEY_D ke_next Key D Next song KEY_E KEY_A KEY_LONG_PRESS ke_rewind Key E with Key A rewind KEY_E KEY_B KEY_LONG_PRESS ke_forward Key E with Key B fast forward KEY_C KEY_D KEY_LONG_ONESHOT ke_powerOff Only one event after long press 0 ke_null End of key mappings Load own key mapping void main currentKeyMap myKeyMap Use own key mapping Note that if there is b...

Страница 25: ...lays Only the service that delivers a sectorful of data from a storage device is changed while rest of the ROM functionality remains the same The image below demonstrates the disk data flow of VS1000 MassStorage USB block interface Flash Mapper Logical Disk wear levelling Flash Physical Physical disk interface minifat Read only FAT filesystem register __i0 u_int16 buffer register __a u_int32 secto...

Страница 26: ...nly when the VS1000 is in player mode it does not write to the logical disk If you want to attach your own device to the USB bus as a mass storage device you need to write a mapper interface that has functions for reading and writing erasing 512 byte sectors Then you need to write a function that publishes the interface with name map initializes the USB handler probably by calling InitUSB USB_MASS...

Страница 27: ... to set SPI to MASTER 16BIT FSYNC not Idle xCS low define SPI_MASTER_16BIT_CSLO PERIP SPI0_CONFIG SPI_CF_MASTER SPI_CF_DLEN16 SPI_CF_FSIDLE0 void InitSpi SPI_MASTER_8BIT_CSHI PERIP SPI0_FSYNC 0 Frame Sync is used as an active low xCS PERIP SPI0_CLKCONFIG SPI_CC_CLKDIV 1 1 Spi clock divider 1 PERIP GPIO1_MODE 0x1f Set SPI pins to be peripheral controlled void EESingleCycleCommand u_int16 cmd SPI_MA...

Страница 28: ...xCS back to high return 0 Disk image is prommed to EEPROM at sector 0x80 onwards leaving the first 64 kilobytes 1 erasable block free for boot code define FAT_START_SECTOR 0x80 This function will replace ReadDiskSector functionality auto u_int16 MyReadDiskSector register __i0 u_int16 buffer register __a u_int32 sector PERIP GPIO1_MODE 0x1f Set SPI pins to be peripheral controlled EEReadBlock secto...

Страница 29: ...olds pointers to the descriptors A system hook vector called InitUSBDescriptors can be used to set your own descriptors 7 5 1 Descriptor data format Mostly because the USB has its roots in the 8 bit oriented PC 80x86 architecture all USB traffic is transmitted byte by byte When values that have more than 8 bits such as 16 bit integers or 32 bit integers are transmitted they are transmitted in the ...

Страница 30: ...L_NUMBER_LENGTH 2 2 8 0x03 1 8 You can 2 8 put any 3 8 numbers you 4 8 like here over the 1 2 3 and 4 0x3000 0x3000 0x3000 0x3000 Last 8 digits of serial 0x3000 0x3000 0x3000 0x3000 number will be calculated here This is the new Device Descriptor See the USB specification Note that since VS_DSP is 16 bit Big Endian processor tables MUST be given as byte swapped 16 bit tables for USB compatibility ...

Страница 31: ...e DT_DEVICE myDeviceDescriptor const u_int16 bHexChar16 swapped Unicode hex characters 0x3000 0x3100 0x3200 0x3300 0x3400 0x3500 0x3600 0x3700 0x3800 0x3900 0x4100 0x4200 0x4300 0x4400 0x4400 0x4500 void main void u_int16 i u_int32 mySerialNumber 0x1234abcd Unique serial number Put unique serial number to serial number descriptor for i 5 i 13 i mySerialNumberStr i bHexChar16 mySerialNumber 28 mySe...

Страница 32: ... SPI EEPROM with an EEPROM programmer A valid boot record starts with identifier 0x564C5349 V L S I and contains blocks of binary data that are to be stored at specified addresses A boot record that is loaded via the SPI bus must have an execution command as the last block Description of the block format is in the datasheet if it should be needed for some special purpose 8 0 2 Using a VS1000 Devel...

Страница 33: ...TER 0x01 define SPI_EEPROM_COMMAND_READ 0x03 define SPI_EEPROM_COMMAND_WRITE 0x02 macro to set SPI to MASTER 8BIT FSYNC Idle xCS high define SPI_MASTER_8BIT_CSHI PERIP SPI0_CONFIG SPI_CF_MASTER SPI_CF_DLEN8 SPI_CF_FSIDLE1 macro to set SPI to MASTER 8BIT FSYNC not Idle xCS low define SPI_MASTER_8BIT_CSLO PERIP SPI0_CONFIG SPI_CF_MASTER SPI_CF_DLEN8 SPI_CF_FSIDLE0 macro to set SPI to MASTER 16BIT FS...

Страница 34: ...tes SpiSendReceive dptr SPI_MASTER_8BIT_CSHI SpiWaitStatus addr 32 u_int16 SpiReadBlock u_int16 blockn u_int16 dptr SpiWaitStatus SPI_MASTER_8BIT_CSLO SpiSendReceive SPI_EEPROM_COMMAND_READ SpiSendReceive blockn 1 0xff Address 15 8 blockn 6 0 0 SpiSendReceive 0 Address 7 0 00000000 SPI_MASTER_16BIT_CSLO u_int16 i for i 0 i 256 i dptr SpiSendReceive 0 SPI_MASTER_8BIT_CSHI return 0 This routine prog...

Страница 35: ... puthex sectorNumber puts SpiWriteBlock sectorNumber minifatBuffer sectorNumber fclose fp Programming complete minifatBuffer 0 0 fputs Reading first 2 words of EEPROM stdout SpiReadBlock 0 minifatBuffer puthex minifatBuffer 0 puthex minifatBuffer 1 fputs stdout putchar minifatBuffer 0 8 putchar minifatBuffer 0 0xff putchar minifatBuffer 1 8 putchar minifatBuffer 1 0xff if minifatBuffer 0 0x564c mi...

Страница 36: ...using a nand flash is somewhat more complicated than using an eeprom To ensure proper operation a nand flash chip must be programmed with a valid VLSI ID record in the beginning of block 0 VS1000 looks for the ID record and adjusts the nand access parameters according to the ID record information If the VLSI boot id V L S I 0x564C5349 is successfully read in the beginning of block 0 the ID record ...

Страница 37: ...s has an erasable block size of 28 512 bytes 128 KiB has an overall size of 219 512 bytes 256 MiB needs 70 ns wait states The parameters x 0x50 led bin nand rec instruct that executable code starts at address 0x0050 linked program image is in led bin boot record should be written to nand rec Output such as the following can be expected from coff2nandboot NandType 3 Large Page 5 byte addr 128kB blo...

Страница 38: ...shown by Windows This feature can be used for initial programming of the nand flash since at the first boot up of a new VS1000 device with an empty nand flash the VLSI ID is not yet programmed into the nand flash and thus the RAM disk appears Later on when the nand flash is programmed and its contents need to be updated the nand flash detection can be prevented by pulling CS1 low when powering up ...

Страница 39: ...dSuffixes bootFiles Only read IMG files if OpenFile 0 0 Open first IMG file on ramdisk j ReadFile mallocAreaX 0 2 0x1000 2 if j 0 goto fail Could not read from the file else goto fail OpenFile did not find any IMG file from the ramdisk File is now read to mallocAreaX and j contains its length struct FsNandPhys ph nandType mallocAreaX 2 nandType from imgfile struct FsNandPhys ph waitns 200 Set 200 ...

Страница 40: ...play pause stop speaker usb cabinet Additional symbols can be defined in RAM The low bytes of u_int16 fontData contain the low end ASCII shapes and variable width symbols Figure 6 VS1000 variable width symbols u_int16 fontPtrs contains the starting offsets of pixel data for each character The high bytes of u_int16 fontData contain katakana and fixed width special sym bols Figure 7 VS1000 fixed wid...

Страница 41: ...YSTEM controls the internal voltage regulator and clock divider of VS1000 Set ting the clock divider while PLL is not used clock multiplier 1 makes the system run at considerably slower clock rate conserving the system power Setting bad voltage values can cause malfuntion and or even physically harm the device or in case of IOVDD even other devices attached to the I O Pins The default values in re...

Страница 42: ... State of Power Button Play Pause pin SCISTF_ANADRV_PDOWN 3 Analog Output Driver power down control SCISTF_ANA_PDOWN 2 Analog Core bias power down control SCISTF_REGU_CLOCK 1 Clock in new regulator voltage values SCISTF_REGU_SHUTDOWN 0 Regulator Shutdown control 12 2 4 USB detection USB detection and device attachment detachment are handled using the System Con troller Actual USB data traffic is h...

Страница 43: ...ly cut down power consumption This is especially useful when some basic operation is needed such as the capability to recover from USB suspend or resume after low power PAUSE mode but battery life needs to be extended The PLL must not be used when divide by 256 is active The PLL tries and fails to lock to a frequency below PLL minimum Switch off PLL set 1 x clock multiplier before setting SCISYSF_...

Страница 44: ... value the input data 1 0 state of pin can always be read from the GPIOn_IDATA register See section Interruptable General Purpose IO Switching a pin to GPIO mode can be used to disable data flow from a pin to a peripheral function The following peripheral input signal values are set when the corresponding pin is in GPIO mode Peripheral Function Input Signal Values When pin is in GPIO Mode GPIO Fun...

Страница 45: ... The DAC interpolator frequency control and PLL controller are controlled using the same register pair FREQCTLH and FREQCTLL Output sample rate is derived from the rollover frequency of a 20 bit interpolator accumulator Its accumulation rate is specified by ifreq The maximum value for ifreq is 0x80000 Note that the DAC and thus also the interpo lator clock is not controlled by the PLL see VS1000 S...

Страница 46: ...s virtually zero the PLL is said to be in lock This means that the output frequency of the VCO is stable and reliable The PLL locked status can be checked by generating a high active pulse writing first 1 then 0 to pll lock test and reading pll lock read Pll lock read is set to 1 along with the high level of pll lock test and to 0 whenever the PLL falls out of lock So if the 1 remains in pll lock ...

Страница 47: ... 12 000 MHz Register Values Result SCI_SYSTEM 15 SCI_STATUS 15 FREQCTLH 9 FREQCTLH 8 FREQCTLH 7 4 Registers SCI_SYSTEM 15 XTALI divide by 2 SCI_STATUS 15 XTALI divide by 256 FREQCTLH 9 Use PLL FREQCTLH 8 Divide PLL input clock by 2 FREQCTLH 7 4 PLL rate control 1 1 0 0 0000 0 02344 MHz 23 438 kHz Lower CVDD possible 0 1 0 0 0000 0 04688 MHz 1 0 0 0 0000 6 MHz 0 0 0 0 0000 12 MHz 0 0 1 1 0010 18 MH...

Страница 48: ...de usage The ROM code in VS1000 has the following usage for PLL The clock rate is selected to be 12 MHz by default 48 MHz when USB is connected and variable between 12 and 42 MHz when Ogg Vorbis is playing DAC rate is set to 44100 Hz when in the USB audio mode When Vorbis is playing the sample rate is set to the sample rate specified in the Ogg file Rev 0 20 2011 10 04 Page 48 90 ...

Страница 49: ...R_MASK Data clear 0 mask 8 r w 0 BIT_CONF Bit engine config 0 and 1 9 r w 0 BIT_ENG0 Bit engine 0 read write 10 r w 0 BIT_ENG1 Bit engine 1 read write 14 2 1 Data Direction GPIOx_DDR The data direction register DDR configures the directions of each of the 16 I O pins A bit set to 1 in the DDR turns the corresponding I O pin to output mode while a bit set to 0 sets the pin to input mode The registe...

Страница 50: ...g bit in the interrupt pending source register INT_PEND 14 2 5 Rising Edge Interrupt Enable GPIOx_INT_RISE If a bit the rising edge interrupt enable register INT_RISE is set to 1 a rising edge in the corresponding pin even when configured as output will set the corresponding bit in the interrupt pending source register INT_PEND 14 2 6 Interrupt Pending Source GPIOx_INT_PEND If any of the bits in t...

Страница 51: ...IT_CONF Bits Name Bits Description GPIO_BE_DAT1 15 12 Data bit selection 0 15 for bit engine 1 GPIO_BE_IO1 11 8 I O bit selection 0 15 for bit engine 1 GPIO_BE_DAT0 7 4 Data bit selection 0 15 for bit engine 0 GPIO_BE_IO0 3 0 I O bit selection 0 15 for bit engine 0 14 2 10 Bit Engine 0 Read Write GPIOx_BIT_ENG0 When writing a value to the bit engine 0 register the data bit specified in the configu...

Страница 52: ...E General purpose IO Port 0 bit 13 GPIO0 14 CS2 21 General purpose IO Port 0 bit 14 VS1000 I O Controller 1 pins and peripheral functions GPIO Ident LQFP Pin Function GPIO1 0 XCS 22 SPI XCS General Purpose I O Port 1 bit 0 GPIO1 1 SCLK 23 SPI CLK General Purpose I O Port 1 bit 1 GPIO1 2 SI 24 SPI MISO General Purpose I O Port 1 bit 2 GPIO1 3 SO 25 SPI MOSI General Purpose I O Port 1 bit 3 GPIO1 4 ...

Страница 53: ... NFDIO 0 7 XCS SCLK SI and SO GPIO1 0 4 are used for SPI EEPROM boot if XCS is high during power on During play mode GPIO1 2 and GPIO1 3 are used for play pause and random play indication TX and RX are normally used for the serial debugging connection Rev 0 20 2011 10 04 Page 53 90 ...

Страница 54: ...uage handler routine Enable Reg 0 IRQ Source 0 Int Origin 0 Global Enable Write Global Disable Write upint Vector Generation and Interrrupt Request Logic 5 Int_vector ack IRQ Source 31 Enable Reg 31 Int origin 31 Global Intr Enable Figure 9 Interrupt Controller Block Diagram 15 1 Registers Interrupt Controller registers prefix INT_ Reg Type Reset Abbrev Description 0 r w 0 ENABLEL0 Interrupt Enabl...

Страница 55: ... core next This happens whenever two interrupt sources request interrupts at the same time or when interrupts become enabled after an interrupt handler routine or part of code where the interrupts have been disabled 15 1 2 Origin INT_ORIGIN 0 1 If an interrupt source requests an interrupt the corresponding bit in the interrupt ori gin register ORIGIN0 or ORIGIN1 will be set to 1 If an interrupt so...

Страница 56: ..._GLOB_DIS and INT_GLOB_EN to ma nipulate the value of this register 15 1 5 Global Disable INT_GLOB_DIS A write of any value to global disable register increases the global interrupt enable disable counter by one If the counter is zero interrupt signal generation is enabled When the interrupt arbitrator generates an interrupt request for VS_DSP core it automatically in creases the counter The user ...

Страница 57: ...0 INTV_GPIO1 10 I O Pin Controller 1 15 3 VS1000 ROM code usage The ROM code in VS1000 has the following usage for interrupts DAC interrupt handles feeding of samples from audio FIFO to DAC registers UART RX interrupt is used for starting the ROM monitor If you perform stdio opera tions in your program you should disable RX interrupt during at least fread to prevent monitor to be erroneously trigg...

Страница 58: ...mpedance state When the slave s chip select is activated it turns MISO to an output and when it starts receiving SCLKs it behaves as defined in the slave s specification xCS Chip Select Every slave requires its own chip select Without the chip select signal a slave may not listen to what happens on the SPI bus Although widely used SPI is not a real standard Because of this there are many different...

Страница 59: ...ay reading a value for a given number of clock cycles after a given clock edge making it possible to make SPI implementations that are not dependent of the output clock edge of a slave device with the price of decreased maximum SPI speed The most typical SPI configuration is such that 8 bit transfers are written MSB first to the bus at falling clock edges and read at a rising clock edges When a tr...

Страница 60: ...external xCS o1 7 o1 6 o1 5 o1 4 o1 3 o1 2 o1 1 o1 0 o2 7 o2 7 o2 6 i1 7 i1 6 i1 5 i1 4 i1 3 i1 2 i1 1 i1 0 i2 7 SPI_CF_MASTER 0 SPI_CF_DLEN 8 SPI_CF_FSIDLE 0 MOSI SAMPLING POINTS external SPI_CC_CLKPOL 0 SPI_CC_CLKPHSE 0 Figure 13 Example SPI Timing Slave Mode In slave mode the SPI clock SCLK is created externally MOSI SCLK and xCS are inputs and MISO is only an output when xCS is active Otherwis...

Страница 61: ...ization is reversed 16 3 Registers SPI registers prefix SPIx_ Reg Type Reset Abbrev Description 0 r w 0 CONFIG 10 0 Configuration 1 r w 0 CLKCONFIG Clock configuration 2 r w 0 STATUS 7 0 Status 3 r w 0 DATA Sent received data 4 r w 0 FSYNC SSI Sync data in master mode 5 r w 0 DEFAULT Data to send slave if SPI_ST_TXFULL 0 16 3 1 Main Configuration SPIx_CONFIG SPIx_CONFIG Bits Name Bits Description ...

Страница 62: ...ampling clock would thus be f 12MHz 2 3 1 1 5MHz SPI_CC_CLKPOL reverses the clock polarity In master mode the inverter is imple mented as the last thing in the output clock data chain In slave mode it is imple mented as the first thing in the input clock data chain See Figure 14 for details If SPI_CC_CLKPOL is clear the data is read at rise edge and written at fall edge if SPI_CC_CLKPHASE is clear...

Страница 63: ...l SPI_ST_TXRUNNING is set if the transmitter shift register is in operation SPI_ST_TXURUN is set if an external data transfer has been initiated in slave mode and the transmit data register has not been loaded with new data to shift out This bit has to be cleared manually Note Because TX and RX status bits are implemented as separate entities it is rela tively easy to make asynchronous software im...

Страница 64: ... based routine and turning chip select off when the device becomes idle 16 5 Changes from 1 2 A default data register is added If in slave mode there is no data to send when it is needed SPI_ST_TXFULL is 0 the default data is sent and SPI_ST_TXURUN is set like before In addition to receive and transmit data registers another set of FIFO registers are added In normal mode these are not used If SPI_...

Страница 65: ... default player application uses the SPI data lines SI and SO in GPIO mode as LED controls 16 7 Effect of Clock Multiplier Note that the clock multiplier affects SPI speed In VS1000 ROM you can read the current clock multiplier setting in global variable clockX Here s a line of code that sets the SPI clock speed taking the clock multiplier into account PERIP SPI0_CLKCONFIG SPI_CC_CLKDIV clockX 1 R...

Страница 66: ...enable active low NFRD Read enable active low NFDIO 8 bit data bus sampled at rising edge of NFRD and written at falling edge of NFWR NFRDY Ready xBusy signal from flash chip This signal must be at logic HIGH state before read or write operation is started command address or data trans action NFRDY requires external 10 kOhm pull up resistor The nand flash IO signals can be read at any time through...

Страница 67: ...ata buffer in bursts from 1 to 32 bytes at a time Block diagram with the main registers is shown in the next figure The architecture has timing control logic which controls the flash operation delay of each write read This logic controls the NFWR NFRD and NFCE signal toggling NFWR and NFRD pulses are always symmetric Without wait states each write read cycle takes two master clock cycles When wait...

Страница 68: ...ration mode in read write cycles int enable 7 Interrupt enable nf sreset 6 Resets the controller waitstates 5 0 Number of wait states in read write cycles Waitstates delays the read write operation by 1 n 1 n master clock cycles where n is the number of wait states I e The flash read write enable low and high times are both delayed 17 3 2 Line and Column parity registers NFLSH_LPL bits Name Bits D...

Страница 69: ...a dbuf is low Data buffer reads writes can be done in 16 consecutive clock cycles It must be noted that when the read mode dsp rd wrd set is selected it takes one clock cycle for the control to transfer the first word from data buffer to dreg Therefore it is recommended that the read mode is set ecc reset enable disable as the nand flash operation is started 17 3 4 Interface control towards physic...

Страница 70: ...te buffer memory is not changed 17 3 6 ECC counter register NFLSH_ECC_CNT bits Name Bits Description ecc cnt 7 0 Calculated ecc words data is processed in 16 bit format Ecc cnt register counts the 16 bit words that are read or written to dreg This information is required when lpl lph and cp are calculated The register is updated only when the ecc is enabled ecc ena 1 In write operation the registe...

Страница 71: ...nd Write Transaction Sym Parameter CLKI cyc Min 48MHz Max 48MHz Tcles Command latch enable setup time 1 41 6ns Tcleh Command latch enable setup time 1 41 6ns Tcled ALE inactive to CLE active delay 1 41 6ns Tces NFCE active to NFWR active delay 1 20 8ns 20 8ns Tceh NFWR inactive to NFCE inac tive delay 1 20 8ns 20 8ns Twl Write enable low time 1 WS 41 6ns Twh Write enable high time 1 WS 41 6ns Tdos...

Страница 72: ...te Transaction Sym Parameter CLKI cyc Min 48MHz Max 48MHz Taled CLE inactive to ALE active delay 1 41 6ns Tales Address latch enable setup time 1 41 6ns Taleh Address latch enable setup time 1 41 6ns Tces NFCE active to NFWR active delay 1 20 8ns 20 8ns Tceh NFWR inactive to NFCE inac tive delay 1 20 8ns 20 8ns Twl Write enable low time 1 WS 20 8ns Twh Write enable high time 1 WS 20 8ns Tdos NFDIO...

Страница 73: ... 48MHz Tclei CLE inactive to NFCE active delay 1 41 6ns Talei ALE inactive to NFCE active delay 1 41 6ns Tces NFCE active to NFRD active delay 1 20 8ns 20 8ns Tceh NFRD inactive to NFCE inac tive delay 1 20 8ns 20 8ns Twed NFWR inactive to NFCE ac tive delay 1 41 6ns Trl Read enable low time 1 WS 20 8ns Trh Read enable high time 1 WS 20 8ns Tdis NFDIO data in setup time 15ns Tdih NFDIO data in hol...

Страница 74: ...meter CLKI cyc Min 48MHz Max 48MHz Tclei CLE inactive to NFCE active deley 1 41 6ns Talei ALE inactive to NFCE active deley 1 41 6ns Tces NFCE active to NFWR active delay 1 20 8ns 20 8ns Tceh NFWR inactive to NFCE inac tive delay 1 20 8ns 20 8ns Tred NFRD inactive to NFCE ac tive delay 1 41 6ns Twl Write enable low time 1 WS 20 8ns Twh Write enable high time 1 WS 20 8ns Tdos NFDIO data out setup t...

Страница 75: ... internal clock for each subsequent access The remaining 504 bytes of the first block and a specified number of additional sectors upto total of 16 sectors i e 8192 bytes can contain VS1000 boot code which can be used to load data to X data RAM Y data RAM or instruction RAM and optionally execute code to extend or replace firmware functionality on chip If the FLASH type is not supported by the ROM...

Страница 76: ...ter 18 2 Registers Timer registers prefix TIMER_ Reg Type Reset Abbrev Description 0xC030 r w 0 CONFIG 7 0 Timer configuration 0xC031 r w 0 ENABLE 1 0 Timer enable 0xC034 r w 0 T0L Timer0 startvalue LSBs 0xC035 r w 0 T0H Timer0 startvalue MSBs 0xC036 r w 0 T0CNTL Timer0 counter LSBs 0xC037 r w 0 T0CNTH Timer0 counter MSBs 0xC038 r w 0 T1L Timer1 startvalue LSBs 0xC039 r w 0 T1H Timer1 startvalue M...

Страница 77: ... before the next timer interrupt Also by writing to this register a one shot different length timer interrupt delay may be realized 18 3 Interrupts Each timer has its own interrupt which is asserted when the timer counter underflows 18 4 VS1000 ROM code usage The ROM code in VS1000 has the following usage for timers Timer 0 is used as the System Timer updating a software real time counter that is ...

Страница 78: ...us UARTx_STATUS A read from the status register returns the transmitter and receiver states UARTx_STATUS Bits Name Bits Description UART_ST_FRAMERR 4 Framing Error stop bit was 0 UART_ST_RXORUN 3 Receiver overrun UART_ST_RXFULL 2 Receiver data register full UART_ST_TXFULL 1 Transmitter data register full UART_ST_TXRUNNING 0 Transmitter running UART_ST_FRAMERR is set at the time of stop bit recepti...

Страница 79: ...e transmitter is busy the UART_ST_TXFULL will be set and the byte remains in the transmitter data register until the previous byte has been sent and transmission can proceed 19 2 3 Data High UARTx_DATAH The same as UARTx_DATA except that bits 15 8 are used 19 2 4 Divider UARTx_DIV UARTx_DIV Bits Name Bits Description UART_DIV_D1 15 8 Divider 1 0 255 UART_DIV_D2 7 0 Divider 2 6 255 The divider is s...

Страница 80: ...atus bit 2 receive data register full is set and status bit 2 old state is copied to bit 3 receive data overrun After that the receiver returns to idle state to wait for a new start bit Status bit 2 is zeroed when the receiver data register is read RS232 communication speed is set using two clock dividers The base clock is the processor master clock Bits 15 8 in these registers are for first divid...

Страница 81: ...as 16 possible start locations for outgoing packets at 128 byte 64 address intervals note that all data addressing in VS1000 is based on 16 bit words 20 2 Registers Universal Serial Bus Controller Registers Address Register Function 0xC080 USB_CONFIG USB Device Config 0xC081 USB_CONTROL USB Device Control 0xC081 USB_STATUS USB Device Status 0xC082 USB_RDPTR Receive buffer read pointer 0xC083 USB_W...

Страница 82: ...k for start of frame USB_STF_RX 13 Interrupt mask for receive data USB_STF_TX_READY 12 Interrupt mask for transmitter holding register empty USB_STF_TX_EMPTY 11 Interrupt mask for transmitter empty idle USB_STF_NAK 10 Interrupt mask for NAK packet sent to host usb configured 0 Configured 0 1 transition loads dtogg host and dtogg device Software should write 1 to usb configured bit when completing ...

Страница 83: ...nter 0xC083 USB_RDPTR bits Name Bits Description USB_RDPTR 15 0 Packet Read Pointer This buffer marks the index position of the last word that the DSP has successfully read from the receive packet buffer DSP should control this register and update the position after each packet it has read from the receive buffer After reset this register is zero 20 2 5 USB_WRPTR Receive buffer write pointer 0xC08...

Страница 84: ...sts IN data for that endpoint Scanning the txpkt ready bit merely allows software to prepare the next packet to be sent even before the previous packet has been sent to the PC The start addr field is index to a 64 word boundary in the transmit buffer memory area The actual memory location that start addr corresponds to is calculated by packet start address USB_SEND_MEM start addr 64 which in VS100...

Страница 85: ... able to achieve this without problems but delays of several milliseconds such as for sending debug messages etc can cause problems with this clause which result in random hang ups of the USB communication with the PC If care is taken to process the packets in the correct order most if not all USB transactions can perfectly well cope with delays of several seconds In practice the PC waits patientl...

Страница 86: ...d for transmission and the USB_EP_SEND register can be loaded with informa tion about the next sendable packet if any To get information about when the packet has actually been transmitted to the PC the Transmitter Idle in xmit empty bit of the endpoint s USB_EP_ST register can be polled or the corresponding interrupt used 20 3 3 How to know that the PC is expecting data During software developmen...

Страница 87: ...SB reset occurs OR a time out occurs Set out forcestall to 0 In a normal case this would send a single STALL to the control endpoint and leave the endpoint open for the next request If an endpoint s other than 0 Halt feature is set USB Chapter 9 standard request the endpoint should be stalled forcestall set to 1 Mass storage class device can use STALL to end a bulk transfer Axelson J USB Mass Stor...

Страница 88: ...ith a unique one For a NAND flash this could be done easily in the first sector s optional boot code Since the USB descriptorTable default values are loaded at each USB init attacj the most straightforward way to do this would be to hook the DecodeSetupPacket function to load USB descriptorTable 3 and call the RealDecodeSetupPacket in ROM USB related software hooks are void USBHandler USB task han...

Страница 89: ...int16 USBHandler MyUSBHandler or by setting the hook vector directly in the boot record via a Set X Memory directive Note that since VS1000B the blinking LED is implemented in the ROM firmware 20 4 3 Used memory areas The USB transmitting routines in VS1000 ROM are limited to transmitting packets of max 64 bytes Only the first 512 bytes addresses X 0x3000 0x30FF of transmit packet memory is used l...

Страница 90: ...cles Once started the watchdog cannot be turned off Also a write to WDOG_CONFIG doesn t change the counter reload value After watchdog has been activated any read write operation from to WDOG_CONFIG or WDOG_DUMMY will invalidate the next write operation to WDOG_RESET This will prevent runaway loops from resetting the counter even if they do happen to write the correct number Writing a wrong value ...

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