PKP
VS1000 P
ROGRAMMER
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S
G
UIDE
VSMPG
13
PLL controller
v1.0 2006-05-10
13.1
General
The Phase-Locked Loop (PLL) controller is used to generate clock frequencies that are
higher than the incoming (crystal-based) clock frequency. The PLL output is used by the
CPU core and some peripherals.
Configurable features include:
•
VCO Enable/Disable
•
Select VCO or input clock to be output clock
•
Route VCO frequency to output pin
•
Select PLL clock multiplier
13.2
DAC Interpolator control
The DAC interpolator frequency control and PLL controller are controlled using the
same register pair FREQCTLH and FREQCTLL. Output sample rate is derived from the
rollover frequency of a 20-bit interpolator accumulator. Its accumulation rate is specified
by ifreq.
The maximum value for ifreq is 0x80000. Note that the DAC (and thus also the interpo-
lator) clock is not controlled by the PLL (see “VS1000 System Controller” and “Overview
of VS1000 Clocking” ).
13.3
Registers
Register map is shown in the next table.
13.3.1
Interpolator Rate (low part)
FREQCTLL bits
Name
Bits
Description
ifreq[15:0]
15:0
Bits 15..0 of the interpolator accumulation rate
Rev. 0.20
2011-10-04
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