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17.2
Block Diagram
Figure 15: Simplified Nand Flash Interface Block Diagram.
The nand flash controller consists of the memory interface signal generation unit and
ECC calculation and logging unit. These units can operate separately from each other.
The peripheral implements a memory mapped interface that generates the control sig-
nals for flash memory read/write operation. It also calculates and logs the parity bit
information from one read/write block. The block size is not limited but the byte counter
is only 9 bits. Reads/writes can be done one at a time or from a 32-byte data buffer in
bursts from 1 to 32 bytes at a time. Block diagram with the main registers is shown in
the next figure.
The architecture has timing control logic which controls the flash operation delay of each
write/read. This logic controls the NFWR, NFRD and NFCE signal toggling. NFWR and
NFRD pulses are always symmetric. Without wait states each write/read cycle takes two
master clock cycles. When waitstates are set to 1 each cycle takes 2+2 master clock
cycles. I.e. Each operation takes (wai1) * 2 master clock cycles. Waitstates can
be set from 0 to 63 (6-bit register). For LCDs the chip select in write mode can be set to
toggle between bytes.
The 32-byte buffer memory consists of 16 addresses, 16 bits each. In the byte-wide bus
operations, the high 8 bits (MSB) are transferred first.
Rev. 0.20
2011-10-04
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