Vlsi VS1000, Руководство программиста

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PKP
VS1000 P
ROGRAMMER
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UIDE VSMPG
13.3.2 Interpolator Rate (high part) and PLL control
FREQCTLH bits
Name Bits Description
pll-lock-read 13 0=lock failed since last test
pll-lock-test 12 1:Sets pll-lock-read to 1 to start lock test
vco-out-ena 11 Route VCO to GPIO pin (VS1000:second cs
pin)
use-pll 9 1:System clock is VCO / 0:System clock is inclk
pll-in-divide 8 divide inclk by 2 (for 1.5, 2.5 or 3.5 x clk)
pll-ratectl 7:4 PLL rate control
ifreq[19:16] 3:0 Bits 19..16 of the interpolator accumulation rate
For comprehensive reference on the function of the clock routing bits, see section
“Overview of VS1000 Clocking” below.
At the core of the PLL controller is the VCO, a high frequency oscillator, whose oscil-
lation frequency is adjusted to be an integer multiple of some input frequency. As the
name “Phase-Locked Loop” suggests, this is done by comparing the phase of the input
frequency against the phase of a signal which is derived from the VCO output through
frequency division.
If the system is stable, e.g. the comparison phase difference remains virtually zero, the
PLL is said to be “in lock”. This means that the output frequency of the VCO is stable
and reliable.
The PLL locked status can be checked by generating a high-active pulse (writing first “1”
, then “0”) to pll-lock-test and reading pll-lock-read. Pll-lock-read is set to “1” along with
the high level of pll-lock-test and to “0” whenever the PLL falls out of lock. So if the “1”
remains in pll-lock-read, PLL is in sync.
The PLL controller gets its input clock from the System Controller and its operation
optimized for frequencies around 12..13 MHz. If you activate clock dividers in the System
Controller to get a slow master clock, you should turn the PLL off before (also switch off
analog before setting a clock of less than 10 MHz).
Note that USB requires 48.0 MHz for packet sending/receiving.
It’s recommended to change the PLL rate in small steps and wait for the PLL to stabilize
after each change. For diagnostic purposes, the PLL clock output (VCO) can be routed
to an I/O pin so it can be scanned with an oscilloscope.
Bits [7:4] (pll-ratectl) control PLL multiplication rate. PLL multiplier is (pll-r 1).
When pll-ratectl is 0, the VCO is powered down and output clock is forced to be input
clock (same as use-pll = 0).
Rev. 0.20 2011-10-04
Page 46(90)