30: Configuring Terminal Server
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© Virtual Access 2017
GW7304 Series User Manual
Issue: 1.9
Page 284 of 336
Web: RTS control mode
UCI: tservd.@port[0].rts_control_mode
Opt: rts_control_mode
Defines RTS line control modes. Only displayed if Atmel USB
serial card is enabled and port mode is X21.
auto
RTS set to on when port is open. Off when the
port is closed.
on
RTS always on.
off
RTS always off.
app
RTS controlled by the application.
ontx
In HDLC mode RTS is on during frame
transmission.
Web: Synchronous rate
UCI: tservd.@port[0].sync_speed
Opt: sync_speed
Defines the synchronous speed in bps. Set to 0 for external
clock. If not set to 0 an internal clock is used. Only displayed if
Atmel USB serial card is enabled.
64000
64 kbps
Range
2048000; 1024000; 768000; 512000; 384000;
256000; 128000; 19200; 9600
Web: Invert receive clock
UCI: tservd.@port[0].sync_invert_rxclk
Opt: sync_invert_rxclk
Defines receive clock inversion. Normal clock data is sampled on
falling edge. Inverted clock data is sampled on rising edge. Only
displayed if Atmel USB serial card is enabled.
0
Normal
1
Invert
Web: Invert transmit clock
UCI: tservd.@port[0].sync_invert_txclk
Opt: sync_invert_txclk
Defines transmit clock inversion. Normal clock data transmitted
on falling edge. Inverted clock data transmitted on rising edge.
Only displayed if Atmel USB serial card is enabled.
0
Normal
1
Invert
Web: RX MSBF
UCI: tservd.@port[0].sync_rx_msbf
Opt: sync_rx_msbf
Defines whether most significant bit is received first. Only
displayed if Atmel USB serial card is enabled.
0
Receive least significant bit first.
1
Receive most significant bit first.
Web: TX MSBF
UCI: tservd.@port[0].sync_tx_msbf
Opt: sync_tx_msbf
Defines whether most significant bit is transmitted first. Only
displayed if Atmel USB serial card is enabled.
0
Transmit least significant bit first.
1
Transmit most significant bit first.
Web: RX data delay
UCI: tservd.@port[0].sync_rxdata_dly
Opt: sync_rxdata_dly
Defines the number of bit positions to delay sampling data from
the detecting clock edge. Only displayed if Atmel USB serial card
is enabled.
0
Range
Web: TX data delay
UCI: tservd.@port[0].sync_txdata_dly
Opt: sync_txdata_dly
Defines the number of bit positions to delay output of data from
the detecting clock edge. Only displayed if Atmel USB serial card
is enabled.
0
Range
Web: Dual X.21 card bit reverse
UCI: tservd.@port[0].bit_reverse
Opt: bit_reverse
Enables bit reversal of all bits in 8 byte word during transmission.
0
Normal.
1
Reverse.
Web: Dual X.21 card DTE TT Invert
UCI: tservd.@port[0].dte_tt_inv
Opt: dte_tt_inv
Enables X.21 TT clock signal inversion.
0
Normal.
1
Invert.
Web: Dual X.21 card DCE TCLK Invert
UCI: tservd.@port[0].dce_tclk_inv
Opt: dce_tclk_inv
Enables X.21 DCE TCLK signal inversion.
0
Normal.
1
Invert.
Web: Dual X.21 card DCE RCLK Invert
UCI: tservd.@port[0].dce_rclk_inv
Opt: dce_rclk_inv
Enables X.21 DCE RCLK signal inversion.
0
Normal.
1
Invert.