FPGA Registers
Lion (VL-EPMe-42) Programmer’s Reference Manual
4
FPGA Registers
FPGA I/O Space
The FPGA is mapped into I/O space on the LPC bus. The address range is mapped into 64 byte I/O
window.
FPGA access: LPC I/O space
FPGA access size: All 8-bit byte accesses (16-bit like registers are aligned on 16-bit word boundaries
to make word access possible in software but the LPC bus still splits the accesses into two 8-bit
accesses)
FPGA address range: 0xC80 to 0xCBF (64-byte window)
The three 8254 timers only require four bytes of addressing and are located at the end of the 64-byte I/O
block. The only requirement is that the base address must be aligned on a 4-byte block. Table 4 lists the
FPGA’s I/O map.
Table 3: FPGA I/O Map
Address Range
Device
Size
0xC80 – 0xCBB
FPGA registers
60 bytes
0xCBC – 0xCBF
8254 timer address registers
4 bytes
3
