FPGA Registers
Lion (VL-EPMe-42) Programmer’s Reference Manual
19
Table 15: MISCSR2 – Misc. Control Register #2
Bit
Identifier
Access
Default
Description
7
RESERVED
RO
0’s
Reserved – Writes are ignored. Reads always return 0
6
W_DISABLE
R/W
0
Used to control the W_DISABLE (Wireless Disable) signal going to the
PCIe Mincard:
0 – W_DISABLE signal is not asserted (Enabled)
1 – W_DISABLE signal is asserted (Disabled)
Note:
There are other control sources that can be configured to control
this signal and if enabled the control becomes the “OR” of all sources
5
ETHOFF1
R/W
0
Used to disable the Ethernet controller #1 (controls the ETH_OFF#
input to the I210-IT):
0 – Ethernet controller is enabled (On)
1 – Ethernet controller is disabled (Off)
4
ETHOFF0
R/W
0
Used to disable the Ethernet controller #0 (controls the ETH_OFF#
input to the I219 Ethernet PHY):
0 – Ethernet Phy controller is enabled (On)
1 – Ethernet Phy controller is disabled (Off)
3
RESERVED
RO
0’s
Reserved – Writes are ignored. Reads always return 0
2
RESERVED
RO
0’s
Reserved – Writes are ignored. Reads always return 0
1
RESERVED
RO
0’s
Reserved – Writes are ignored. Reads always return 0
0
RESERVED
RO
0’s
Reserved – Writes are ignored. Reads always return 0
MISCR3 – Miscellaneous Control Register #3
This register sets the SMBus addresses on the 4-Port PCIe Switch.
Table 16: MISCR3 – Misc. Control Register #3
Bits
Identifier
Access
Default
Description
7-4
Reserved
RO
0
Reserved. Writes are ignored; reads always return 0.
3
Reserved
RO
0
Reserved. Writes are ignored; reads always return 0.
2
PBRESET
R/W
---
When written to, this will do the same thing as pushing the reset
button, which could be useful for a software-initiated watchdog.
0 – No action
1 – Activate the reset push-button
Note:
Because this generates a reset that will reset this register, it
isn’t likely a value of a ‘1’ can ever be read-back, so it is somewhat
“write-only”.
1-0
Reserved
RO
0
Reserved. Writes are ignored; reads always return 0.
