FPGA Registers
Lion (VL-EPMe-42) Programmer’s Reference Manual
21
AUXIN – AUX GPIO I/O Input Status Register
This registers sets the AUX GPIO input value. It will read the input value regardless of the setting on the
direction (that is, it always reads the input). This reads the actual state of the GPIO pin into the part.
Table 20: AUXIN – AUX GPIO Input Status Register
Bits
Identifier
Access
Default
Description
7-0
IN_GPIOIO[8:1]
RO
N/A
Reads the GPIOx input status. For each bit:
0 – Input de-asserted if polarity not-inverted;
asserted if polarity inverted
1 Input asserted if polarity not-inverted;
de-asserted if polarity inverted
AUXIMASK – AUX GPIO Interrupt Mask Register
This is the interrupt mask registers for the AUX GPIOs and the interrupt enable selection. The reset type is
Platform Reset because interrupts always have to be setup after exiting sleep states.
Table 21: AUXICR – AUX GPIO Interrupt Mask Register
Bits
Identifier
Access
Default
Description
7-0
IMASK_GPIO[8:1]
R/W
0
GPIOx interrupt mask. For each bit:
0 – Interrupt disabled
1 – Interrupt enabled
AUXISTAT – AUX GPIO I/O Interrupt Status Register
Table 22: AUXISTAT – AUX GPIO Interrupt Status Register
Bits
Identifier
Access
Default
Description
7-0
ISTAT_GPIO[8:1]
RW/C
N/A
GPIOx interrupt status. A read returns the interrupt status. Writing
a ‘1’ clears the interrupt status.
This bit is set to a ‘1’ on a transition from low-to-high
(POL_DIOx=0) or high-to-low (POL_DIOx=1).
