VersaLogic Lion VL-EPMe-42, Справочное руководство

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FPGA Registers
Lion (VL-EPMe-42) Programmer’s Reference Manual 13
Table 10: TCR – 8254 Timer Control Register
Bit Identifier Access Default Description
7 TMR5GATE
R/W
0
Controls the “gate” signal on 8254 timer #5 when not using an external
gate signal:
0 – Gate on signal GCTC5 is disabled
1 – Gate on signal GCTC5 is enabled
Always set to 0 when configuring timer modes. Set to a ‘1’ if using
external clocking. It can be turned on and off when using internal
clocking.
6 TMR4GATE
R/W
0
Controls the “gate” signal on 8254 timer #4 when not using an external
gate signal:
0 – Gate on signal GCTC4 is disabled
1 – Gate on signal GCTC4 is enabled
Always set to 0 when configuring timer modes. Set to a ‘1’ if using
external clocking. It can be turned on and off when using internal
clocking.
5 TMR3GATE
R/W
0
Controls the “gate” signal on 8254 timer #3 when not using an external
gate signal:
0 – Gate on signal GCTC3 is disabled
1 – Gate on signal GCTC3 is enabled
Always set to 0 when configuring timer modes. Set to a ‘1’ if using
external clocking. It can be turned on and off when using internal
clocking.
4 TM45MODE
R/W
0
Mode to set timers #4 and #5 in:
0 – Timer #4 and #5 form one 32-bit timer controlled by timer #1 signals
1 – Timer #4 and Timer #5 are separate 16-bit timers with their own
control signals.
Almost always used in 32-bit mode especially when TMRFULL is a ‘0’
(the 16-bit timer #5 if of limited use)
3 TM4CLKSEL
R/W
0
Timer #4 Clock Select:
0 – Use internal 4.125 MHz clock (derived from PCI clock)
1 – Use external ICTC4
Timer #5 is always on internal clock if configured as a 16-bit clock
2 TM3CLKSEL
R/W
0
Timer #3 Clock Select:
0 – Use internal 4.125 MHz clock (derived from PCI clock)
1 – Use external ICTC3 assigned to Digital I/O
1 TMROCTST R/W 0
Debug/Test Only: Used to derive OCTCx outputs with TIMxGATE
signals for continuity testing only:
0 – Normal operation
1 – Drive OCTCx outputs with corresponding TMRxGATE control
registers (e.g., OCTC4 with TMR4GATE) for continuity testing.
0 Reserved R/W 0 Reserved. Writes are ignored; reads always return 0.