VersaLogic Blackbird VL-EPU4562, Справочное руководство, Страница: 9 / 47

EPU-4562 Programmer’s Reference Manual 4
FPGA Registers
This chapter describes the FPGA registers.

Table 2 (beginning on the following page) lists all 64 FPGA registers

Table 3 (refer to page 8) through Table 48 provide bit-level information on the individual
FPGA registers
Register Access Key
Key:
R/W Read/Write
RO Read-Only
R/WC Read-Status/Write-1-to-Clear
WO Write-Only
ROC Read-Only and clear-to-0 after reading
RSVD
Not implemented. Returns 0 when read. Writes are
ignored
Reset Status Key
Reset Status Key
POR Power-on reset (only resets one time when input power comes on)
Platform Resets prior to the processor entering the S0 power state (that is, at power-on and in sleep states)
resetSX
•
If AUX_PSEN is a '0' in MISCSR1 (default setting), then this is the same as the Platform reset.
•
If AUX_PSEN is programmed to a '1', then it is the same as the Power-On Reset (POR).
n/a Reset doesn't apply to status or reserved registers
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