SU320CSX
4110-0446, Rev. B
Page 23 of 96
© 2016 UTC Aerospace Systems
Date Printed: 5-Dec-2016
This document does not contain any export controlled technical data.
4.
Principles of Operation
4.1.
Focal Plane Array Operation
The SUI CSX camera family uses the SU320AB4-1.7T1 Indium Gallium Arsenide (InGaAs) focal plane
array (FPAs). These FPAs have 320 x 256 pixels on a 12.5 µm pitch. The FPAs consist of an InGaAs
photodiode array hybridized to a CMOS readout using indium bump bonds. The photodiode array is a
backside illuminated device (where light first passes through the substrate before interacting with the
sensing media) with typical quantum efficiency (QE) and responsivity shown, respectively: the graphs
differ by the power dependency on the wavelength of the photon. For Visible-InGaAs and NIR/SWIR, the
substrate is thinned to allow shorter wavelength light to reach the light sensitive region of the photodiode.
The blocking InP substrate media is removed with respect to diode operation in a separate semiconductor
fabrication process. Photon detection is performed directly by the InGaAs layer in photovoltaic operation.
A converting phosphor or similar layer is not used.
Figure 8. Typical Quantum Efficiency of SUI backside illuminated FPAs.
The CMOS readouts are “active pixel” devices in which the photocurrent is buffered, amplified and
stored in each pixel. A simplified pixel schematic is shown in Figure 9. Each pixel contains a buffered
gate modulated (B-GMOD) input circuit for converting current to voltage with continuously adjustable
gain. In this circuit, the photodiode bias voltage is set through internally generated DSUB and VREF bias
voltages. The photodiode current flows through M0 with a proportional amount of current mirrored in
M1. The ratio of the currents through M1 and M0 is controlled though the externally set VBIAS and
VGAIN voltages. The camera internally provides all bias voltages necessary for operation of the focal
plane array.
