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The TRAM Standard
TMB M 711 Transputer Motherboard User Manual
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The notReset and notAnalyse arriving at the slave’s up port are also
sent to the slave’s subsystem port, but in this case the signals are
logically OR-ed with the analyse and reset signals of the boards’s
subsystem. This means that a board may be reset/analysed by its
own master OR by the master of that master. E.g.
Boardd can be
controlled by either
boardb
or
boarda
in figure 27, above.
The notError signal is treated similarly, but flows in the opposite
direction. The error from a module on a motherboard is passed to the
up port of that motherboard. It is logically OR-ed with any notError
signal arriving at that boards down port. This allows error signals to
propagate back to the master - it also means that ANY processor in
a subsystem can send an error to the master. E.g. processors on
boardc/d can send error back to their master ( boardb ) in figure 27,
above.
The notError signal arriving at a subsystem port is not propagated to
the up port, but is handled by that board. It is assumed that a
subsystem master can handle errors in its own subsystem.
3.3.3.4 Subsystem Registers
When the source of control is a transputer module in site 0 of some
motherboard then the transputer on that module has control of the
subsystem via its subsystem pins. These pins are driven by
subsystem registers on the TRAM which are in turn mapped into the
transputer’s memory map.
For 32 bit transputers the memory mapping is as follows:
The operation of the registers is as follows:
• Writing a 1 into bit 0 of SubsystemResetLatch asserts
subsystemReset ;
• Writing a 0 into bit 0 of SubsystemResetLatch deasserts
subsystemReset
;
Register Mode Hardware byte address
SubsystemResetLatch Write Only #00000000
SubsystemAnalyseLatch Write Only #00000004
SubsystemError Read Only #00000000
Table 1: memory-mapped registers