Transtech Transputer, Руководство пользователя

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The TMB17 Motherboard
TMB M 711 Transputer Motherboard User Manual
139
10.3.2.3 Rx Status
A one read from bit 0 of offset 02h indicates that a byte of data is
available to be read from the RX Data register.
10.3.2.4 Tx Status
A one read from bit 0 of offset 03h indicates that a byte of data can
be written to the Tx Data register.
10.3.2.5 Rx Level
The value read from offset 18h indicates the number of bytes
available to be read from the Rx Data FIFO. To ensure a coherent
value is read a 16bit Word read should be used to read this register.
10.3.2.6 Tx Level
The value read from offset 1Ch indicates the number of bytes of
space free in the Tx Data FIFO. To ensure a coherent value is read
a 16bit Word read should be used to read this register.
10.3.2.7 Reset/error
Writing a one to bit 0 of offset 10h will force Reset to be sent to
module 0 and the FIFO link interface, a 0 must be written to clear the
Reset. Reading bit 0 will return the state of module 0 error flag.
10.3.2.8 Analyse
Writing a one to bit 0 of offset 11h will force Analyse to be sent to
module 0, a 0 must be written to remove Analyse.
10.3.3 PCI Configuration
Programmers should note that Transtech’s PCI SIG Vendor ID is
1278 hex. The TMB17 has a Device ID of 1001hex.
10.4 Network Configuration
This section provides an overview of network configuration on the
TMB17. It describes the wiring of the electronic link switch, the patch
area and shows the relationship between these and the edge
connector.
10.4.1 Electronic Link Configuration
This section describes the organization of the electronic link switch,
the IMSC004.