Transmeta Crusoe TM5500, Руководство по проектированию систем

Страница: 70 / 130

July 17, 2002
70
SDR Memory Design
5.3.4 Read Timing
The processor memory controller has no information concerning the distance (and therefore delay) to and
from the memory chips, but it must know when to expect valid data that is read from memory. The board
designer must communicate this information by providing a carefully calibrated delay loop to resynchronize
the data to the clock. The processor CLKOUT and SLKIN signal pins provide this function. The critical
components of read timing compensation using CLKOUT and CLKIN are detailed in Figure 11 below.
The delay of the CLKIN line is equal to the round-trip delay of the read command and data. This delay has
three components:
• The delay of the clock trace.
• The delay of the shortest data trace.
• A factor to allow for different capacitive loading of the clock and feedback traces, and for capacitive
loading of the data trace.
These elements are described as delays, and not as lengths. Signals on the surface of a board travel at a
different velocity (~150 pS/in) from the traces inside the board (~180 pS/in), due to the influence of the
dielectric constant of the surrounding air.
Note also that these delays are from chip to chip. The trace delay on the SODIMM must be part of this
calculation.
Looking at each component of the delay, the first two elements are easily understood. The delay of the clock
trace is necessary to account for the timing of the signal to the chip. The delay of the data is needed to
account for the return trip. The shortest data line is used to provide sufficient setup time without compromising
hold time.
The loading of the clock and data can be quite different, and failure to account for this loading difference will
skew the timing. The clock will almost always have four loads, and though actual loads must be determined
from the manufacturer specifications, one load is usually about 2-4 pF.
The delay due to clock and data loading is determined by the amount of loading, the drive current, and the
termination resistance. Rather than calculate this in each instance, it is often simpler to rely on past
experience to determine delay values. Experience has shown these capacitive delays cause a skew of
approximately 500 pS. Therefore, a 500 pS delay element must be added to the clock feedback.
Figure 11: Read Timing Compensation
SDRAM Feedback Clock - SD_CLKIN
R
s
SD_CLKIN
Z
B
Z
B
Z
B
Z
B
SD_CLKOUT
R
T
L0
Delay of Clock Trace
Delay of Shortest Data Trace
Clock Loading
L0
MAX MIN
0.00" 1.20"
Z
B
Minimum Data Loading
Delay