Transmeta Crusoe TM5500, Руководство по проектированию систем

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July 17, 2002
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DDR Memory Design
4.5 DDR Memory Interface Design Guidelines
The DDR SDRAM interface operates at frequencies of 100-133 MHz. Use standard high-speed design,
layout, and routing practices. Some specific guidelines in DDR memory layout are provided below.
• To achieve the most ideal DDR layout possible, the TM5500/TM5800 DDR interface and memory layout
should be completed first, with trace lengths as short as possible, before other sections of the design
layout complicate DDR signal routing.
• A nominal DDR SDRAM layout must have trace lengths less than 4”.
• Data traces are routed in groups. Each group consists of one DDR_DQS, one DDR_DQMB, and eight
DDR_DQ lines.
• The DDR_DQ and DDR_DQMB signals within each group must be routed such that the maximum
difference in their lengths is 0.4” or less. The DDR_DQS signal for the group must have a length that is
within 0.1” of the longest other trace in that group. The length of all DQS signals must be within a 2”
range and within 1” of the length of the clocks.
• The differential clocks (DDR_CLKA/A#, DDR_CLKB/B#) must be routed such that the length of each
clock signal to each SDRAM is the same length within 0.05”. The length of the clocks must be within 1.0”
of all DQS signals.
• All byte groups may be swapped with other byte groups and all data bits within each byte may be
swapped to facilitate meeting length requirements.
• Characteristic impedance should be 60
Ω
± 10%.
• Layout components as shown in the example below. The components should be exactly on top of one
another in the following specified order. Devices 0-1 get differential clock pair DDR_CLKA/DDR_CLKA#
and devices 2-3 get differential clock pair DDR_CLKB/DDR_CLKB#.