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PLACE R11 CLOSE TO SOURCE, PROCESSOR BALL V6

TM5800 Design Guide

Custom

A

Basil

Thursday, November 29, 2001

2

5

TM5800 SDR Interface

3940 Freedom Circle
Santa Clara, CA. 95054
(408) 919-3000

DOCUMENT#

Copyright (C) 1995-2001 Transmeta
Corporation.  All rights reserved.
This document contains confidential and
proprietary information of Transmeta
Corporation.  It is not to be disclosed or used
except in accordance with applicable
agreements.  This copyright notice does not
evidence any actual or intended publication of
such document.

Page

of

Title:

Document Number:

Size:

Revision:

Date:

Author:

Project:

SDR_CLKOUT

SDR_CLKIN

SDR_DQ62_R

SDR_DQ1_R

SDR_DQ46_R

SDR_DQ20_R
SDR_DQ21_R

SDR_DQ24_R

SDR_DQ63_R

SDR_DQ53_R

SDR_DQ55_R

SDR_DQ41_R

SDR_DQ31_R

SDR_DQ0_R

SDR_DQ42_R

SDR_DQ12_R

SDR_DQ5_R

SDR_DQ39_R

SDR_DQ52_R

SDR_DQ47_R

SDR_DQ61_R

SDR_DQ7_R

SDR_DQ28_R

SDR_DQ48_R

SDR_DQ36_R

SDR_DQ18_R

SDR_DQ8_R

SDR_DQ23_R

SDR_DQ57_R

SDR_DQ50_R

SDR_DQ59_R
SDR_DQ60_R

SDR_DQ51_R

SDR_DQ15_R

SDR_DQ45_R

SDR_DQ26_R

SDR_DQ4_R

SDR_DQ34_R

SDR_DQ40_R

SDR_DQ17_R

SDR_DQ56_R

SDR_DQ38_R

SDR_DQ6_R

SDR_DQ10_R

SDR_DQ32_R

SDR_DQ54_R

SDR_DQ35_R

SDR_DQ37_R

SDR_DQ9_R

SDR_DQ29_R

SDR_DQ16_R

SDR_DQ14_R

SDR_DQ44_R

SDR_DQ33_R

SDR_DQ25_R

SDR_DQ43_R

SDR_DQ19_R

SDR_DQ49_R

SDR_DQ13_R

SDR_DQ30_R

SDR_DQ27_R

SDR_DQ11_R

SDR_DQ3_R

SDR_DQ2_R

SDR_DQ58_R

SDR_DQ22_R

SDR_CKE_MUX1_R

SDR_BA1_R

SDR_CS2_R#

SDR_A8_R

SDR_A10_R

SDR_CS0_R#

SDR_A5_R

SDR_A1_R

SDR_BA0_R

SDR_DQM2_R

SDR_DQM5_R

SDR_A0_R

CLK_SDR1_R

SDR_MWE_R#

NC_U1_K4

SDR_CAS_R#

NC_U1_K3

NC_U1_L5

SDR_A12_R

SDR_DQM6_R

SDR_DQM3_R

SDR_DQM1_R

CLK_SDR0_R

SDR_CS1_R#

CLK_SDR2_R

SDR_A3_R

SDR_A2_R

SDR_A4_R

SDR_RAS_R#

SDR_A9_R

SDR_DQM0_R

SDR_A11_R

NC_U1_K5

SDR_A7_R

SDR_A6_R

CLK_SDR3_R

SDR_CKE_MUX0_R

SDR_DQM4_R

SDR_DQM7_R

SDR_CS3_R#

SDR_MWE#

SDR_DQ14

SDR_DQ57

SDR_DQ37

SDR_DQ41

SDR_DQ3

SDR_DQ59

SDR_DQ34

SDR_DQ51

SDR_CAS#

SDR_DQ22

SDR_DQ58

SDR_A4

SDR_DQ35

SDR_BA0

SDR_DQM0

SDR_DQ38

SDR_CS2#

SDR_DQ8

SDR_RAS#

SDR_DQ39

SDR_DQ45

SDR_DQ42

SDR_DQ33

SDR_DQ63

SDR_A5

SDR_A12

SDR_DQ20

CLK_SDR2

SDR_DQM6

SDR_DQ27

SDR_DQM1

SDR_DQ25

SDR_A7

SDR_DQ9

SDR_DQ31

SDR_DQ48

SDR_A11

SDR_DQ2

SDR_DQ62

SDR_DQ24

SDR_DQ26

SDR_DQ32

SDR_DQ0

SDR_DQ60

SDR_DQ4

SDR_DQ40

SDR_DQM5

SDR_DQ43

SDR_DQ52

SDR_DQM3

SDR_A6

SDR_DQ50

SDR_DQ47

SDR_DQ12

SDR_CS3#

SDR_DQM7

SDR_DQ15

SDR_DQ55

SDR_DQ46

SDR_DQ23

SDR_DQ53

SDR_DQ54

CLK_SDR3

SDR_A1

SDR_DQ11

SDR_DQ36

SDR_DQ44

SDR_DQ30

SDR_DQ21

CLK_SDR1

SDR_DQ7

SDR_DQ17

CLK_SDR0

SDR_DQM4

SDR_DQ49

SDR_DQ61

SDR_DQ18

SDR_A0

SDR_DQ1

SDR_CS1#

SDR_DQ56

SDR_DQM2

SDR_CKE_MUX0

SDR_DQ29

SDR_A8

SDR_DQ16

SDR_DQ5

SDR_DQ19

SDR_DQ28

SDR_DQ10

SDR_A2

SDR_DQ13

SDR_CS0#

SDR_A10

SDR_DQ6

SDR_CKE_MUX1

SDR_BA1

SDR_A3

SDR_A9

RN47A

33

1

8

RN45B

33

2

7

RN36A

33

8

1

RN43B

33

2

7

RN28A

33

1

8

RN31D

10

4

5

RN32B

33

2

7

RN36C

33

3

6

RN39B

10

2

7

RN33B

10

2

7

RN48B

33

2

7

RN27C

33

3

6

RN48C

33

3

6

RN45D

33

4

5

RN35B

33

2

7

RN44C

10

3

6

RN29C

33

3

6

RN40C

33

3

6

RN31C

33

3

6

RN39C

33

3

6

RN38B

10

2

7

RN33D

10

4

5

RN48D

33

4

5

RN27A

33

1

8

RN49C

33

3

6

RN43C

33

3

6

RN34C

33

3

6

RN47D

33

4

5

RN29B

33

2

7

RN42B

10

2

7

RN43A

33

1

8

RN30C

33

3

6

RN38A

33

1

8

RN38D

10

4

5

R13

22

1

2

RN46A

33

8

1

RN31B

10

2

7

RN28B

33

2

7

RN37D

10

4

5

RN45C

33

3

6

SDR

(PART 2 OF 5)

U1B

Crusoe BGA474

P3
N4
V5
P4
N5
M1
P1
N1
P2
N2
M2
K1

W5

AB4
AB5
AA5

Y5

AC4
AD3
AD2
AC2
AC1
AD1
AA4
AA3

Y4
Y3
W4
G4
G6
G5
E6
F5
D5
E5
D6
F4
F3
E3
E4
D4
B5
C5
C4

AA6
AC5
AD5
AD4
AE3
AE5
AE4
AE2
AB2
AB1
AA2
AA1

Y2
Y1
W2
W1
F1
F2
E1
D1
E2
C1
D2

B1

B2

B3

A4

A2

B4

A3

A5

C2

U1
U4
H4
H3
U5
U2
H2
H1

T4
T3
T1
T2

M3
M4
M5
L4
L5
K3
K4
K5

J2
J1

L2
L1

V4

AB6

V6

R5

P5

K2

S_A0

S_A1

S_A2

S_A3

S_A4

S_A5

S_A6

S_A7

S_A8

S_A9

S_A10

S_A11

S_DQ0

S_DQ1

S_DQ2

S_DQ3

S_DQ4

S_DQ5

S_DQ6

S_DQ7

S_DQ8

S_DQ9

S_DQ10

S_DQ11

S_DQ12

S_DQ13

S_DQ14

S_DQ15

S_DQ16

S_DQ17

S_DQ18

S_DQ19

S_DQ20

S_DQ21

S_DQ22

S_DQ23

S_DQ24

S_DQ25

S_DQ26

S_DQ27

S_DQ28

S_DQ29

S_DQ30

S_DQ31

S_DQ32

S_DQ33

S_DQ34

S_DQ35

S_DQ36

S_DQ37

S_DQ38

S_DQ39

S_DQ40

S_DQ41

S_DQ42

S_DQ43

S_DQ44

S_DQ45

S_DQ46

S_DQ47

S_DQ48

S_DQ49

S_DQ50

S_DQ51

S_DQ52

S_DQ53

S_DQ54

S_DQ63

S_DQ62

S_DQ61

S_DQ60

S_DQ59

S_DQ58

S_DQ57

S_DQ56

S_DQ55

S_DQMB0

S_DQMB1

S_DQMB2

S_DQMB3

S_DQMB4

S_DQMB5

S_DQMB6

S_DQMB7

S_CS0#

S_CS1#

S_CS2#

S_CS3#

S_CLK0

S_CLK1

S_CLK2

S_CLK3

S_CLK4

S_CLK5

S_CLK6

S_CLK7

S_CKE0

S_CKE1

S_BA0

S_BA1

S_CAS#

S_CLKIN

S_CLKOUT

S_RAS#

S_WE#

S_A12

RN44A

10

1

8

RN47B

33

2

7

RN33C

33

3

6

RN42A

33

1

8

RN32D

33

4

5

RN38C

33

3

6

R14

22

1

2

RN41D

10

4

5

R11

33

1

2

RN26A

33

8

1

RN30D

10

4

5

RN49A

33

1

8

RN37B

10

2

7

RN28D

33

4

5

RN44D

33

4

5

RN35D

33

4

5

RN46B

33

2

7

RN37A

33

1

8

RN42C

33

3

6

RN32C

33

3

6

R15

22

1

2

RN41B

10

2

7

RN47C

33

3

6

RN29D

10

4

5

RN30A

33

1

8

RN41A

33

8

1

RN36B

10

2

7

RN31A

33

8

1

RN45A

33

8

1

RN35C

33

3

6

RN37C

33

3

6

RN46D

33

4

5

RN43D

33

4

5

RN40B

10

2

7

RN26B

33

2

7

RN34A

33

8

1

RN30B

10

2

7

RN48A

33

1

8

RN29A

33

1

8

RN41C

33

3

6

RN36D

10

4

5

RN32A

33

1

8

RN39A

33

8

1

RN34D

10

4

5

RN49D

33

4

5

RN27B

33

2

7

RN26C

33

3

6

RN46C

33

3

6

RN40D

10

4

5

RN44B

33

2

7

RN35A

33

8

1

RN42D

33

4

5

RN28C

33

3

6

RN33A

33

1

8

R12

22

1

2

RN40A

33

1

8

RN39D

10

4

5

RN34B

10

2

7

RN27D

33

4

5

RN49B

33

2

7

RN26D

33

4

5

Содержание Crusoe TM5500

Страница 1: ...TM5500 TM5800 System Design Guide July 17 2002...

Страница 2: ...without notice Transmeta products have not been designed tested or manufactured for use in any application where failure malfunction or inaccuracy carries a risk of death bodily injury or damage to t...

Страница 3: ...ore Power Supply Example 25 3 1 3 PLL Power Supply 30 3 1 4 I O Power Supplies 33 3 1 5 Decoupling Capacitors 34 3 2 Power Supply Sequencing 35 3 2 1 Power Sequencing Requirements 35 3 2 2 Power Seque...

Страница 4: ...h ROM Write Protection Circuit 93 6 5 3 Combined BIOS CMS Parallel ROM Interface 96 6 6 Southbridge 98 6 6 1 Qualified Southbridge Devices 98 6 6 2 Using CLKRUN 98 6 6 3 Southbridge Schematics 98 6 7...

Страница 5: ...put Control Selector 25 Table 9 MAX1718 DSX Voltage Configuration 26 Table 10 Power Supply Sequencing Timing Specifications 35 Table 11 DDR SDRAM Memory Configurations 51 Table 12 SDR SDRAM Memory Con...

Страница 6: ...July 17 2002 6 List of Tables...

Страница 7: ...m Layer 58 Figure 10 Physical SDRAM Configurations 68 Figure 11 Read Timing Compensation 70 Figure 12 Adjustment of CLKIN Delay 71 Figure 13 Optimum Placement and Routing 72 Figure 14 Sub optimal Plac...

Страница 8: ...July 17 2002 8 List of Figures...

Страница 9: ...R SDRAM memory into a design Chapter 5 SDR Memory Design provides design guidelines and layout requirements for incorporating SDR SDRAM memory into a design Chapter 6 System Design Considerations desc...

Страница 10: ...signal names used in the Data Book and other hardware specific materials can be different from those used on the reference schematics This section shows the terms used in the System Design Guide and...

Страница 11: ...iption C0 Normal Active power state with processor executing instructions C1 Auto Halt Sleep state entered by processor executing HALT instruction C2 Quick Start Sleep state requiring chipset hardware...

Страница 12: ...ventions used in the schematics S4 Suspend to Disk STD Current processor state is suspended and saved to non volatile disk All power supplies except _ALWAYS are off S5 Soft Off System is turned off Al...

Страница 13: ..._IRDY PCI_LOCK PCI_PAR CPU_RST CLK_PCI_TM PCI_PERR PCI_STOP PCI_TRDY PCI_REQ 5 0 PCI_SERR SUSC SUSB PWRGOOD PCI_FERR CPU_IGNNE INIT INTR NMI SMI CPU_CLK CPU_STPCLK SUSPEND PCI_RST CPU_RST SYS_RST conn...

Страница 14: ...translator Isolation Signal isolation is used to ensure that CKE signals to the SDRAMs remain stable during processor power transitions Since the processor does not have a suspend power well output si...

Страница 15: ...July 17 2002 15 Example System Block Diagram and Schematics 2 2 Processor Schematics The following pages show TM5500 TM5800 processor reference schematics...

Страница 16: ...0 DDR_BA1 DDR_CAS DDR_DQS 7 0 DDR_A 12 0 DDR_CS2 DDR_CKE_MUX0 CLK_DDRA DDR_CS1 DDR_CS0 DDR_MWE DDR_CKE_MUX1 CLK_DDRB DDR_DQM 7 0 DDR_CS3 V2_5 RN12A 24 1 8 RN17B 24 2 7 RN1A 10 1 8 RN7C 24 3 6 RN22C 24...

Страница 17: ...Q61 SDR_DQ18 SDR_A0 SDR_DQ1 SDR_CS1 SDR_DQ56 SDR_DQM2 SDR_CKE_MUX0 SDR_DQ29 SDR_A8 SDR_DQ16 SDR_DQ5 SDR_DQ19 SDR_DQ28 SDR_DQ10 SDR_A2 SDR_DQ13 SDR_CS0 SDR_A10 SDR_DQ6 SDR_CKE_MUX1 SDR_BA1 SDR_A3 SDR_A...

Страница 18: ...UN PCI_GNT1 PCI_DEVSEL PCI_STOP PCI_REQ0 PCI_REQ5 PCI_REQ4 PCI_REQ1 PCI_REQ2 PCI_REQ3 PCI_HLD V3_3 V3_3 V3_3 V3_3 V3_3 V3_3 R 10K 1 2 RN50C 10K 3 6 RN54C 10K 3 6 RN52D 10K 4 5 RN51B 10K 2 7 RN51C 10K...

Страница 19: ...NT PWRGOOD SROM_CS0 CLK_CPU EPROMA1 SROM_SIN CPU_INIT SROM_SCLK TDM_TMS CPU_STPCLK DIODE_CATHODE SRCLK CPU_IGNNE TDM_SROM_CS1 CPU_FERR TDM_TRST DEBUG_INT CPU_SMI TDM_TCK TDM_SDA TDM_TDO TDM_RST DIODE_...

Страница 20: ...OVDD IOVDD IOVDD IOVDD IOVDD IOVDD IOVDD IOVDD IOVDD IOVDD IOVDD IOVDD IOVDD IOVDD IOVDD IOVDD IOVDD IOVDD IOVDD IOVDD IOVDD IOVDD IOVDD IOVDD IOVDD IOVDD IOVDD IOVDD IOVDD25 IOVDD25 IOVDD25 IOVDD25 I...

Страница 21: ...2 System Block Diagram shows the power supplies for each of the major components The power source for all notebook computers is either a battery 20 V or a DC wall adapter of a comparable voltage An in...

Страница 22: ...UST NOT EXCEED 1 5 V OR PERMANENT DEVICE DAMAGE MAY RESULT Table 5 Core Power Supply Requirements for TM5500 TM5800 Processors Specification Value Notes Core voltage range 0 95 1 30 V nominal See Long...

Страница 23: ...bulk capacitors 5 m maximum Combined capacitance of bulk capacitors 800 F minimum nominal 1100 F maximum nominal Distribution resistance from bulk capacitors to processor 2 m maximum Inductor inductan...

Страница 24: ...0 1 0x05 1 50 V 0 0 1 1 0 0x06 1 45 V 0 0 1 1 1 0x07 1 40 V 0 1 0 0 0 0x08 1 35 V 0 1 0 0 1 0x09 1 30 V 0 1 0 1 0 0x0A 1 25 V 0 1 0 1 1 0x0B 1 20 V 0 1 1 0 0 0x0C 1 15 V 0 1 1 0 1 0x0D 1 10 V 0 1 1 1...

Страница 25: ...used to control the output voltage is determined by the ZMODE and SUS input signals These inputs control internal multiplexers that select which register is presented to the DAC to set the output vol...

Страница 26: ...to the TM5500 TM5800 processor core during extended Deep Sleep periods significantly reducing processor leakage power during long intervals of sustained system inactivity The reference design example...

Страница 27: ...n the output voltage which in the reference design example is approximately 0 85 See the MAX1718 data sheet for detailed information on adjusting the output voltage offset 3 1 2 5 Switching Frequency...

Страница 28: ...ing up as required by TM5500 TM5800 power sequencing specifications VGATE has an internal sense circuit to force it high during programmed transitions such as normal LongRun voltage step transitions w...

Страница 29: ...ionofTransmeta Corporation It is nottobedisclosedorused except inaccordancewithapplicable agreements Thiscopyrightnoticedoesnot evidenceanyactualorintendedpublicationof suchdocument Page of Title Docu...

Страница 30: ...t 1 0 V 50 mV across a nominal core operating voltage range of 0 9 V to 1 0 V For transitions in the core voltage e g during LongRun power management voltage steps V_CPU_PLL must settle to within the...

Страница 31: ...rved This documentcontainsconfidentialand proprietaryinformationofTransmeta Corporation It is nottobedisclosedorused except inaccordancewithapplicable agreements Thiscopyrightnoticedoesnot evidenceany...

Страница 32: ...to the processor V_CPU_PLL pin as possible and the V_CPU_PLL GND loop length should be minimized Circuit Operation During operation the V5_0 5 0 V supply to the opamp and V2_5 2 5 V supply to Q1 must...

Страница 33: ...es are derived from V3_3_STR and V2_5_STR care must be taken to ensure the voltages are not glitched when these supplies are turned on Glitching can be minimized by controlling the turn on rise time o...

Страница 34: ...er peripheral decoupling capacitors V_CPU_CORE Underside BGA Decoupling Example BOTTOM SIDE AS SEEN FROM TOP SIDE SHARED VIA TO GND Y10 W10 SHARED VIA TO V_CPU_CORE V11 U10 SHARED VIA TO GND U9 T10 SH...

Страница 35: ...in the figure below System designs for TM5500 TM5800 processors must also meet the power on requirements specified in the Data Book The table below provides timing specifications for the power supply...

Страница 36: ...ch off The current spike may trigger other system level protection circuits or result in I O contention 3 2 2 Power Sequencing Circuit Examples As explained above in Power Sequencing Requirements on p...

Страница 37: ...poration All rightsreserved This documentcontainsconfidentialand proprietaryinformationofTransmeta Corporation It is nottobedisclosedorused except inaccordancewithapplicable agreements Thiscopyrightno...

Страница 38: ...July 17 2002 38 Processor Power Supplies and Power Management 3 3 Power Supply Voltage Supervisor The following page shows a power supply voltage supervisor reference design schematic...

Страница 39: ...tcontainsconfidentialand proprietaryinformationofTransmeta Corporation It is nottobedisclosedorused except inaccordancewithapplicable agreements Thiscopyrightnoticedoesnot evidenceanyactualorintendedp...

Страница 40: ...July 17 2002 40 Processor Power Supplies and Power Management 3 4 POWERGOOD Block Diagram Example The following page shows an example block diagram for possible system POWERGOOD circuits...

Страница 41: ...E SYSTEM LEVEL POWERGOOD TO THE TM5800 CPU AND SOUTHBRIDGE NOTE ENABLE_VIO MANUAL_RST WHEN ENABLE_VIO MANUAL_RST IS HIGH THE CORE VOLTAGE IS AT LEVEL ENABLE_VIO IS THEN USED WITH THE VOLTAGE SEQUENCIN...

Страница 42: ...r the power on sequence are provided here Parameter Description Min Max Diagram Note tvdd_rise Supply delay and rise time 1 1 Refer to Figure 4 and Table 10 for details on power supply sequencing timi...

Страница 43: ...of the notes in the diagrams below Refer to Figure 4 and Table 10 for details on power supply sequencing timing Power On C0 PCI_RST RESET POWERGOOD CPU_CLK PCI_CLK V_CPU_CORE V_CPU_PLL V3_3 V2_5 T1 T2...

Страница 44: ...O cycle that initiates the C3 power state is typically snooped by the processor The processor integrated northbridge must be properly configured to snoop this I O cycle and the power management softwa...

Страница 45: ...C0 3 S typical 5 S maximum T7 State Transition Timing Information Requirements Diagram Note STPCLK assertion to Stop Grant cycle 3 5 S typical 8 S maximum T1 Stop Grant to SLEEP assertion 2 S minimum...

Страница 46: ...Ms into self refresh by the time the I O cycle reaches the power management controller There are no special requirements for the power management signaling between the I O cycle and the removal of mai...

Страница 47: ...ntroller waits 64 S between de asserting the processor SLEEP signal and de asserting the processor STPCLK signal This type of system is expected to have a worst case C3 entrance exit latency of 207 S...

Страница 48: ...rt by ensuring that there is no external activity in the system during the frequency change This is accomplished by flushing any queued PCI or memory writes and force granting the PCI bus to the proce...

Страница 49: ...to account for the regulator settling time The default LongRun power management parameters assume a 64 S settling time which is compatible with the voltage regulators referenced in this document Note...

Страница 50: ...July 17 2002 50 Processor Power Supplies and Power Management...

Страница 51: ...ce The DDR SDRAM controller supports the equivalent of one DIMM one bank only of DDR SDRAM using a 64 bit wide interface The DDR SDRAM interface does not support parity bits The DDR SDRAM can be popul...

Страница 52: ...ter of the Development and Manufacturing Guide for further LongRun configuration and memory frequency information 4 2 Clock Enable Isolation The processor DDR_CKE clock enable signals must be isolated...

Страница 53: ...d 2490 For a DDR_VREF specification of 1 35 V the recommended V2_5 voltage divider network for deriving DDR_VREF is upper resistor tied to V2_5 1960 and lower resistor tied to ground 2320 4 4 1 DDR Re...

Страница 54: ...ed such that the maximum difference in their lengths is 0 4 or less The DDR_DQS signal for the group must have a length that is within 0 1 of the longest other trace in that group The length of all DQ...

Страница 55: ...device placement using both sides of the PCB Figure 6 Recommended 4 Device DDR Memory Chip Placement DDR 2 DDR 3 DDR 0 TM5x00 Processor DDR 1 Top Bottom Place components one over the other on opposit...

Страница 56: ...ide Top Layer Signal Routing The figure below shows the connections from the TM5500 TM5800 processor to the DDR memory on the primary top layer side of the board Figure 7 Recommended 4 Device DDR Memo...

Страница 57: ...sign Internal Layer Signal Routing The figure below shows the connections from the TM5500 TM5800 processor to the DDR memory on an internal layer of the board Figure 8 Recommended 4 Device DDR Memory...

Страница 58: ...Bottom Layer Signal Routing The figure below shows connections from the TM5500 TM5800 processor to the DDR memory on the secondary bottom layer side of the board Figure 9 Recommended 4 Device DDR Mem...

Страница 59: ...59 DDR Memory Design 4 7 DDR SDRAM Schematics The following pages show DDR SDRAM reference schematics Single bank DDR soldered down 2 pages Single bank DDR SODIMM 2 pages DDR clock enable isolation ci...

Страница 60: ...DQ17 DDR_DQ7 DDR_DQS3 DDR_A10 DDR_A7 DDR_DQ30 DDR_DQ31 DDR_A0 DDR_DQ20 DDR_CS0 DDR_DQ16 DDR_MWE DDR_A7 DDR_DQ19 DDR_A10 CLK_DDRA DDR_A2 DDR_BA0 DDR_DQ 63 0 DDR_A 12 0 CLK_DDRA DDR_RAS DDR_DQM 7 0 DDR_...

Страница 61: ...DR_A0 DDR_A8 CLK_DDRB DDR_DQ34 DDR_CS0 DDR_A2 DDR_RAS DDR_RAS DDR_DQ57 DDR_DQ52 DDR_A 12 0 DDR_DQ 63 0 DDR_DQS 7 0 DDR_BA0 DDR_CS0 DDR_CKE0 DDR_RAS CLK_DDRB DDR_CAS DDR_MWE DDR_DQM 7 0 DDRVREF DDR_BA1...

Страница 62: ...DDR_A8 DDR_DQS6 DDR_DQ16 DDR_DQ10 DDR_DQ24 DDR_DQ0 DDR_DQM6 DDR_DQ11 DDR_DQ3 DDR_DQ47 DDR_DQ42 DDR_DQ12 DDR_A10 DDR_CS0 DDR_DQ 63 0 DDR_CKE1 DDR_CS1 CLK_DDRA DDR_DQS 7 0 CLK_DDRA CLK_DDRB SMBCLK DDR_R...

Страница 63: ...1 2 C9 0 1uF 1 2 C3 0 1uF 1 2 J1B 200_SODIMM_DDR 197 199 1 2 3 4 15 16 27 28 38 39 40 51 52 63 64 75 76 87 88 90 103 104 125 126 137 138 149 150 159 161 162 173 174 185 186 9 10 21 22 33 34 36 45 46 5...

Страница 64: ...pt inaccordancewithapplicable agreements Thiscopyrightnoticedoesnot evidenceanyactualorintendedpublicationof suchdocument Page of Title DocumentNumber Size Revision Date Author Project DDR_CKE_MUX1 DD...

Страница 65: ...SDRAM DIMMs can be populated with 64 Mbit 128 Mbit 256 Mbit or 512 Mbit devices All DIMMs must use the same frequency SDRAMs but there are no restrictions on mixing different DIMM configurations into...

Страница 66: ...number of loads the rules are as follows For up to 16 loads the maximum total trace length must be 5 For up to 12 loads the maximum total trace length must be 8 Source termination of 33 at the proces...

Страница 67: ...ignal Termination Series termination is recommended for all signals Termination impedance should be calculated on a per design basis 5 2 4 Miscellaneous Notes If DIMMs are used the serial presence det...

Страница 68: ...ng only JEDEC compliant SODIMMs is very straightforward Place the SODIMMs close together using reverse image connectors routing signals from the processor to the SODIMMs Note that if the SODIMM connec...

Страница 69: ...es not exceed the driver s specified capacity It is important to note that this restriction is an original design limitation The system may well be capable of successfully driving a longer line Howeve...

Страница 70: ...hese delays are from chip to chip The trace delay on the SODIMM must be part of this calculation Looking at each component of the delay the first two elements are easily understood The delay of the cl...

Страница 71: ...mory module is replaced by a different module Code Morphing software could fail to load or operate reliably Another memory solution possibility uses soldered down memory on the system motherboard It i...

Страница 72: ...oard memory on the far side of the SODIMM from the processor yields the optimum routing solution Figure 13 Optimum Placement and Routing Figure 14 Sub optimal Placement Crusoe CPU SODIMM Connector Ter...

Страница 73: ...tors can easily meet a 10 tolerance at no additional cost Termination resistors are sized to match the board impedance to minimize reflections If a characteristic impedance other than 55 is used the t...

Страница 74: ...On Board Memory RT RT L0 L1 L2 MIN MAX MIN MAX MIN MAX TOTAL MIN MAX 0 00 1 10 0 00 4 00 0 10 0 40 0 75 4 00 L3 MIN MAX 0 10 0 40 NOM TOL NOM TOL RT 28 Ohms 10 33 ohms 10 ZB 60 ohms ZB 55 ohms ZB ZB Z...

Страница 75: ...1 40 L0 L1 L2 MIN MAX MIN MAX MIN MAX TOTAL MIN MAX 0 00 1 10 0 00 4 00 0 10 0 40 0 75 4 00 L3 MIN MAX 0 10 0 40 NOM TOL NOM TOL RT 5 Ohms 10 10 ohms 10 ZB 60 ohms ZB 55 ohms ZB ZB ZB ZB ZB Clock Enab...

Страница 76: ...he board stack up to yield the desired characteristic impedance Recalculate termination resistor values as needed 4 Place SDR SDRAM close to the processor no further than 4 from processor preferably o...

Страница 77: ...e length of this trace on the SODIMM is 0 6 1 0 Assume a length of 0 8 on a surface trace The delay on the SODIMM is Using only one bank of x8 parts on the board both CLK 3 and CLK 2 can be used ensur...

Страница 78: ...R_DQ22 CLK_SDR2 SDR_DQ56 SDR_DQ27 SDR_DQ32 SDR_DQ14 SDR_DQ59 SMBDATA SDR_DQ39 SDR_BA1 SDR_DQ48 SDR_DQ42 CLK_SDR3 V3_3_STR V3_3_STR V3_3_STR V3_3_STR V3_3_STR R1 22 1 2 C6 0 1uF 1 2 C11 0 1uF 1 2 C2 0...

Страница 79: ...Q29 SDR_DQ18 SDR_DQM2 SDR_DQ56 SDR_DQ25 SDR_DQ26 SDR_DQ60 SDR_DQ47 SDR_DQ42 SDR_CKE1 SDR_DQ24 SDR_DQ16 SDR_DQM7 SDR_A4 V3_3_STR V3_3_STR V3_3_STR V3_3_STR V3_3_STR R1 22 1 2 C8 0 1uF 1 2 C6 0 1uF 1 2...

Страница 80: ...26 SDR_DQM1 SDR_A9 SDR_CS1 SDR_DQ56 SDR_DQ60 SDR_DQM4 SDR_DQ51 SDR_DQ1 SDR_A1 CLK_SDR1 SMBDATA_SDR1 SDR_DQ49 V3_3_STR V3_3_STR V3_3_STR V3_3_STR V3_3_STR C24 0 1uF 1 2 C17 0 1uF 1 2 C25 0 1uF 1 2 C23...

Страница 81: ...NT Copyright C 1995 2001Transmeta Corporation All rights reserved This documentcontainsconfidentialand proprietaryinformationofTransmeta Corporation It is nottobedisclosedorused except inaccordancewit...

Страница 82: ...pt inaccordancewithapplicable agreements Thiscopyrightnoticedoesnot evidenceanyactualorintendedpublicationof suchdocument Page of Title DocumentNumber Size Revision Date Author Project DDR_CKE_MUX1 DD...

Страница 83: ...ionship between the processor and PCI clocks should be such that the CLK_CPU leads CLK_PCI_TM by 3 3 nS typical The clock traces including CLK_CPU and CLK_PCI_TM from the clock generator to each PCI c...

Страница 84: ...nyactualorintendedpublicationof suchdocument Page of Title DocumentNumber Size Revision Date Author Project PU_CKGEN CLK_R14M V_CKG25 CLK_RPCI_SB PD_CKG24 CLK_RUSB_SB V_CKG33 CKGX1 CLK_RPCI_TM CLK_RCP...

Страница 85: ..._U1_30 NC_U1_36 NC_U1_29 XTL_IN U1_P8 NC_U1_35 U1_23 U1_P42 NC_U1_33 U1_P47 U1_2 NC_U1_32 SMBDATA PCI_STP CLK_14M SUSA CLK_USB_SB CLK_PCI_SB CLK_CPU CLK_PCI_TM SMBCLK CPU_STP V3_3 V3_3 V2_5 L2 68 Ohm...

Страница 86: ...eset Diagram Note During system power up TM5500 TM5800 processors drive the P_PCI_RST pin invalid high when V3_3 3 3 V I O power supply is powered and V_CPU_CORE processor core supply is not powered I...

Страница 87: ...wn in the table below Many of these signals are outputs from the processor and all non DRAM processor outputs are tri stated float during Deep Sleep Table 15 Signal Pull up Pull down Requirements Proc...

Страница 88: ...ing serial ROM chip select 2 When no mode bit ROM is populated use pull up on CFG_SDATA to force Code Morphing software to boot from serial flash ROM use pull down on CFG_SDATA to force Code Morphing...

Страница 89: ...range of system operating configurations Use of the external mode bit ROM is required for guaranteed operation of all production parts For more information see the Development and Manufacturing Guide...

Страница 90: ...and proprietaryinformationofTransmeta Corporation It is nottobedisclosedorused except inaccordancewithapplicable agreements Thiscopyrightnoticedoesnot evidenceanyactualorintendedpublicationof suchdocu...

Страница 91: ...ned together with the system BIOS into a parallel ROM These two Code Morphing software ROM configurations are described below 6 5 1 Serial Flash ROM Interface Code Morphing software can be optionally...

Страница 92: ...blicationof suchdocument Page of Title DocumentNumber Size Revision Date Author Project U2_P3 SROM_CSOUT U2_P11 U2_P13 U2_P12 TDM_SROM_CS0 TDM_SROM_CLK SROM_SOUT SROM_CS0 SROM_SCLK SROM_SIN SROM_WP TD...

Страница 93: ...It ensures that the Code Morphing software boot image is not accidentally overwritten It allows for field upgrades of Code Morphing software should they be needed 6 5 2 1 Circuit Operation The write...

Страница 94: ...ash ROM is not 5 V tolerant Power Since the standard 22LV10 draws at least 70 90 mA from 3 3 V Transmeta recommends a part with a power saving feature be used Many vendors sell 22LV10 parts with power...

Страница 95: ...SROM_SCLK SROM_SOUT SROM_SIN WP WPNEG SEL CS0IN CS1IN CLK DIN CS0OUT CS1OUT CLK DIN CS DOUT SROM_SIN SROM_CS0 SROM_CS1 SROM_SCLK SROM_SOUT 3 3V GPIO 3 3V South Bridge Crusoe ATF22LV10CZ Debug Connect...

Страница 96: ...ility for x86 software applications or viruses to erase the entire ROM including the Code Morphing software portion To protect against unauthorized Code Morphing software erasure the Code Morphing sof...

Страница 97: ...Corporation All rights reserved This documentcontainsconfidentialand proprietaryinformationofTransmeta Corporation It is nottobedisclosedorused except inaccordancewithapplicable agreements Thiscopyri...

Страница 98: ...ith TM5500 TM5800 processors Contact your Transmeta representative for qualification status of other southbridge devices 6 6 2 Using CLKRUN Refer to the following figure for the recommended CLKRUN imp...

Страница 99: ...R PCI_INTE PCI_HLD PCI_FRAME PCI_INTD PCI_HLDA PCI_DEVSEL PCI_CBE3 PCI_INTA PCI_STOP PCI_RST PCI_INTF PCI_CBE2 PCI_PAR Part 1 of 4 PCI IDE Symbol ver 1 U1A M1535 ALI C5 G2 F1 F2 F3 E1 E2 E3 D1 D3 C1 B...

Страница 100: ...0 Y15 V10 W11 Y11 Y10 W12 V11 Y12 B11 T18 E12 D11 N19 N18 M17 V6 BIOSA18 GPO24 CLK_OFF BIOSA17 GPO25 BIOSA16 GPO26 SA15 SD15 EGPIO15 EEGPIO15 SA14 SD14 EGPIO14 EEGPIO14 SA13 SD13 EGPIO13 EEGPIO13 SA12...

Страница 101: ...t Audio Part 3 of 4 U3C M1535 ALI J19 J20 L20 M16 K18 K17 K20 K19 M20 L17 L16 M19 L18 L19 M18 U2 R5 U3 V1 V2 V3 W1 W2 W3 Y1 Y2 T4 R4 W9 Y8 Y9 P5 P4 U1 J2 G1 H3 J4 J3 H1 J5 H2 L1 J1 K5 K1 L2 K3 K2 K4 T...

Страница 102: ...1 2 C5 0 1uF 1 2 C6 0 1uF 1 2 R10 10K 1 2 C12 0 1uF 1 2 C2 0 1uF 1 2 C9 0 1uF 1 2 C4 0 1uF 1 2 Part 4 of 4 Power Ground Miscellaneous U1D M1535 ALI F15 K16 G15 P6 F14 F7 F6 P15 R14 R8 R6 T10 R13 R7 R1...

Страница 103: ...he dedicated THRM input on the southbridge This device is powered from V3_3 Careful layout is required to ensure the lowest noise and greatest accuracy of the thermal sensor diode 6 8 1 Thermal Sensor...

Страница 104: ...t There are a number of rules to ensure minimal noise in the thermal sensor circuits Minimize the distance from the processor to the sensor chip This rule minimizes crosstalk because the parallelism w...

Страница 105: ...rops exponentially with distance If the gradient is too large the two traces are exposed to different field strengths and the common mode rejection of the sensor chip has no effect on this noise Keep...

Страница 106: ...roprietaryinformationofTransmeta Corporation It is nottobedisclosedorused except inaccordancewithapplicable agreements Thiscopyrightnoticedoesnot evidenceanyactualorintendedpublicationof suchdocument...

Страница 107: ...signal The Transmeta Debug Module TDM communicates to the target through a high density 30 pin flex cable known as TDCA The TDCA is shown with connections to the core system The TDM and the debug con...

Страница 108: ...TDM 0 5mm FPC Vertical SMT ZIF 30 contact 52559 3092 http www molex com product ffc 52559 html Vertical style part number molex 0 5mm FPC Right Angle SMT ZIF Top Contact 30 contact 52435 3091 http www...

Страница 109: ...tion It is nottobedisclosedorused except inaccordancewithapplicable agreements Thiscopyrightnoticedoesnot evidenceanyactualorintendedpublicationof suchdocument Page of Title DocumentNumber Size Revisi...

Страница 110: ...July 17 2002 110 System Design Considerations...

Страница 111: ...the plane This results in 0 022 to 0 023 copper between vias under the processor If normal anti pad treatments were allowed the amount of copper under the chip would be severely decreased limiting pro...

Страница 112: ...See layer stack up for copper weight and layer orientation Core and prepreg combinations are optional to the manufacturer unless otherwise specified in the layer stack up Plating all holes and conduc...

Страница 113: ...aints Table 17 Recommended Eight Layer PCB Stackup Signal Layer Material 1 Signal 1 oz copper 2 GND 1 1 oz copper 3 Signal 2 oz copper 4 PWR 1 oz copper 5 GND 2 1 oz copper 6 Signal 3 oz copper 7 GND...

Страница 114: ...mils 6 mils Thru pin to buried blind via 10 mils 6 mils Thru pin to line 5 mils 5 mils Thru pin to shape 5 mils 5 mils SMD pin to SMD pin 5 mils 5 mils SMD pin to test pin 5 mils 5 mils SMD pin to thr...

Страница 115: ...e PCI Net Value CLK Net Value Maximum line width 5 mils 5 mils 5 mils Minimum neck width 5 mils 5 mils 5 mils Maximum neck length 0 mils 0 mils 0 mils Allow on etch subclass Allowed Allowed Allowed T...

Страница 116: ...2002 116 PCB Layout Guidelines 7 4 Footprint and Pin Escape Diagram Figure 24 Mechanical Footprint A 1 AE 19 SILKSCREEN OUTLINE PADSTACK SMT PAD 030 DIA SOLDERMASK OPENING 033 DIA PASTEMASK OPENING 0...

Страница 117: ...DD regulator should meet the following requirements The processor VRDA outputs are open drain and therefore require pull ups If the VRM controller does not have internal pull ups on its VID inputs the...

Страница 118: ...erial should be used 8 V_CPU_CORE CVDD decoupling High frequency at least 8 low ESL ceramic capacitors on the back side of the board directly underneath the processor The case size should be as small...

Страница 119: ...irectional level translator should be Controlled by SUS_STAT1 pin T17 on the iPIIX4 or SUSPEND pin W13 on the ALI 1535 Controlled by the same signal that is connected to the processor SLEEP pin Powere...

Страница 120: ...should connect to pin 2 of the DIP TSOP or pin 3 of the PLCC The CS signal should connect to pins 4 and 5 on the DIP TSOP and pins 5 and 6 on the PLCC None of the pins are 5 V tolerant so the signal...

Страница 121: ...IO should switch 12 V onto the parallel ROM 4 The Maxim thermal sensor should be connected as follows MAX1617 pin 3 to processor pin A18 MAX1617 pin 4 to processor pin B16 MAX1617 alert output to THER...

Страница 122: ...July 17 2002 122 System Design Checklists...

Страница 123: ...LD Data JEDEC Fuse Map and CUPL Source Code 24 Pin TSSOP The following text is the JEDEC file representing the fuse map for the write protection PLD It was produced by the CUPL PLD design compiler for...

Страница 124: ...240 11111111111101111111110111011111 L02272 11111111111111111111111101111111 L02304 11101110111111111111111111110000 L02880 00000000000000000000000011111111 L02912 11111111111111111111111111111111 L02...

Страница 125: ...h to require detection of all 8 bits of the opcode If the chip select is negated after the 8th bit of the opcode the flash device will execute the command with bogus address and data The select input...

Страница 126: ...output enable OE controls on all flip flops Q0 SP b 0 Q1 SP b 0 Q0 OE b 1 Q1 OE b 1 State names and numbers To guard against output glitches the state numbers are assigned so that most transitions on...

Страница 127: ...way out is reset PRESENT NO_PAT_MATCH NEXT NO_PAT_MATCH Only way out is reset Output equations Each chip select is copied from input to output unless the current state is PAT_MATCH and the WP input is...

Страница 128: ...July 17 2002 128 Serial Write protection PLD Data...

Страница 129: ...ion 66 Clock Enable S_CKE isolation 67 signal termination 67 E erase all command 96 F flash serial for Code Morphing software 91 flash serial for Code Morphing software write protection 93 footprint 1...

Страница 130: ...July 17 2002 130 Index...

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