Transmeta Crusoe TM5500, Руководство по проектированию систем

Страница: 51 / 130

July 17, 2002
51
C h a p t e r 4
DDR Memory Design
This chapter provides guidelines for implementing DDR SDRAM memory interface designs for
TM5500/TM5800 processors. Following the recommended DDR memory interface design rules and layout
procedures will result in reliable system designs that maximize performance while minimizing power
consumption. Signal descriptions and timing specifications for the TM5500/TM5800 DDR SDRAM memory
interface can be found in the
Data Book .
4.1 DDR Memory Interface
The DDR SDRAM interface is the highest performance memory interface available on TM5500/TM5800
processors. The DDR controller supports only DDR SDRAM and transfers data at a rate that is twice the clock
frequency of the interface. The DDR SDRAM controller supports the equivalent of one DIMM (one bank only)
of DDR SDRAM using a 64-bit wide interface. The DDR SDRAM interface does not support parity bits.
The DDR SDRAM can be populated with 64-Mbit, 128-Mbit, 256-Mbit, or 512-Mbit devices. For the highest
performance, it is recommended that the DDR SDRAM devices be soldered down to the circuit board, rather
than incorporated on DIMMs. The DDR SDRAM interface supports only x8 or x16 devices. The table below
shows possible TM5500/TM5800 DDR SDRAM configurations.
Table 11: DDR SDRAM Memory Configurations
DDR Device
Size DDR Device
Configuration Devices per
Bank Mbytes per
Bank Maximum
Banks Maximum
Memory Size
64 Mbit 4M x 16 4 32 1 32 Mbytes
8M x 8 8 64 1 64 Mbytes
128 Mbit 8M x 16 4 64 1 64 Mbytes
16M x 8 8 128 1 128 Mbytes
256 Mbit 16M x 16 4 128 1 128 Mbytes
32M x 8 8 256 1 256 Mbytes
512 Mbit 32M x 16 4 256 1 256 Mbytes
64M x 8 8 512 1 512 Mbytes