Toshiba TXZ, Справочное руководство

Страница: 102 / 120

TXZ Family
Flash Memory
2018-06-05
102 / 120
Rev. 2.0
9 C

T RAM store start address (31 to 24) The controller transmits the RAM start address to be
stored in RAM store data by dividing into 4 times as a next
transmit data.
Transmission order is as follows: 1 st byte corresponds to
bit 31 to bit 24 and 4 th byte corresponds to bit 7 to bit 0 of
transfer address. These addresses should be placed in
“0x20000400” through the last address of RAM address.
The target checks receive data. If a receive error exists,
the target sends ACK response data “0x18” indicating
communication error, and then returns to the initial state
waiting for operation command data. If a receive error
does not exist, the target transmits nothing, and waits for
next transmit data.
10 C

T RAM store start address (23 to 16)
11 C

T RAM store start address (15 to 8)
12 C

T RAM store start address (7 to 0)
13 C

T
The number of bytes where the
RAM stores data (15 to 8)
The controller transmits the number of bytes to be
block-transferred. Transmission order is as follows: 1 st
byte corresponds to bit 15 to bit 8 and 2 nd byte
corresponds to bit 7 to bit 0 of transfer address. These
addresses should be placed in “0x20000400” through the
last address of RAM address.
The target checks receive data. If a receive error exists,
the target sends ACK response data “0x18” indicating
communication error, and then returns to the initial state
waiting for operation command data. If a receive error
does not exist, the target transmits nothing, and waits for
next transmit data.
14 C

T
The number of bytes where the
RAM stores data (7 to 0)
15 C

T
A CHECKSUM value of transmit
data (No.9 to 14)
The controller transmits a CHECKSUM value of transmit
data (No.9 to 14).
16 T

C
ACK response to a CHECKSUM
value
Normal: 0x10
Abnormal: 0x11
Communication error: 0x18
The target checks receive data, and it sends ACK
response data.
If a receive error exists, the target sends ACK response
data “0x18” indicating communication error, and then
returns to the initial state waiting for operation command
data.
If a receive error does not exist, the target checks a
CHECKSUM value.
If checking is failed, the target sends ACK response data
“0x11” indicating abnormal state, and then returns to the
initial state waiting for operation command data. If
checking is succeeded, the target sends ACK response
data “0x10” indicating normal state, and then it waits for
next data.
17 C

T RAM store data
The controller transmits data to be stored in RAM from the
controller.
The target receives data to be stored in RAM.
18 C

T
A CHECKSUM value of transmit
data (No.17)
The controller transmits a CHECKSUM value of transmit
data (No.17).
19 T

C
ACK response to CHECKSUM
verification
- Normal: 0x10
- Abnormal: 0x11
- Communication error: 0x18
The target checks receive data, and it sends ACK
response data.
If a receive error exists, the target sends ACK response
data “0x18” indicating communication error, and then
returns to the initial state waiting for operation command
data.
If a receive error does not exist, the target checks a
CHECKSUM value.
If checking is failed, the target responds ACK response
data “0x11” indicating abnormal state, and then returns to
the initial state waiting for operation command data.
If checking is succeeded, the target sends ACK response
data “0x10” indicating normal state and jumps to RAM
store start address (No.9 to 12) as a branch
address.(Note)
Note: A setup of the functions (a port, UART, a timer, RAM, etc.) which the Boot ROM program used is not
initialized.