Toshiba TLCS-870/C1 Series, Руководство пользователя

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Page 21
TMP89FM42
RA001
2.3.4.1 Warm-up counter operation when the oscillation is enabled by the hardware
(1) When a power-on reset is released or a reset is released
The warm-up counter serves to secure the time after a power-on reset is released before the supply
voltage becomes stable and the time after a reset is released before the oscillation by the high-fre-
quency clock oscillation circuit becomes stable.
When the power is turned on and the supply voltage exceeds the power-on reset release voltage,
the warm-up counter reset signal is released. At this time, the CPU and the peripheral circuits are
held in the reset state.
A reset signal initializes WUCCR<WUCSEL> to "0" and WUCCR<WUCDIV> to "11", which
selects the high-frequency clock (fc) as the input clock to the warm-up counter.
When a reset is released for the warm-up counter, the high-frequency clock (fc) is input to the
warm-up counter, and the 14-stage counter starts counting the high-frequency clock (fc).
When the upper 8 bits of the warm-up counter become equal to WUCDR, counting is stopped and
a reset is released for the CPU and the peripheral circuits.
WUCDR is initialized to 0x66 after reset release, which makes the warm-up time 0x66
×
2
9
/fc[s].
Note: The clock output from the oscillation circuit is used as the input clock to the warm-up counter. The
warm-up time contains errors because the oscillation frequency is unstable until the oscillation cir-
cuit becomes stable.
(2) When the STOP mode is released
The warm-up counter serves to secure the time after the oscillation is enabled by the hardware
before the oscillation becomes stable at the release of the STOP mode.
The high-frequency clock (fc) or the low-frequency clock (fs), which generates the main system
clock when the STOP mode is activated, is selected as the input clock for frequency division circuit,
regardless of WUCCR<WUCSEL>.
Before the STOP mode is activated, select the division rate of the input clock to the warm-up
counter at WUCCR<WUCDIV> and set the warm-up time at WUCDR.
When the STOP mode is released, the 14-stage counter starts counting the input clock selected in
the frequency division circuit.
When the upper 8 bits of the warm-up counter become equal to WUCDR, counting is stopped and
the operation is restarted by an instruction that follows the STOP mode activation instruction.
Note 1: When the operation is switched to the STOP mode during the warm-up for the oscillation enabled by the software, the
warm-up counter holds the value at the time, and restarts counting after the STOP mode is released. In this case, the
warm-up time at the release of the STOP mode becomes insufficient. Don't switch the operation to the STOP mode during
the warm-up for the oscillation enabled by the software.
Clock that generates the main system
clock when the STOP mode is acti-
vated
WUCCR<WUCSEL> WUCCR<WUCDIV> Counter input clock Warm-up time
fc Don’t Care
00 fc
2
6
/ fc to 255 x 2
6
/ fc
01 fc / 2
2
7
/ fc to 255 x 2
7
/ fc
10
fc / 2
2
2
8
/ fc to 255 x 2
8
/ fc
11
fc / 2
3
2
9
/ fc to 255 x 2
9
/ fc
fs Don't Care
00 fs
2
6
/ fs to 255 x 2
6
/ fs
01 fs / 2
2
7
/ fs to 255 x 2
7
/ fs
10
fs / 2
2
2
8
/ fs to 255 x 2
8
/ fs
11
fs / 2
3
2
9
/ fs to 255 x 2
9
/ fs