Toshiba TLCS-870/C1 Series, Руководство пользователя

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2. CPU Core
2.3 System clock controller
TMP89FM42
RA001
The hardware control is executed by reset release and the operation mode control circuit when the oper-
ation is switched to the STOP mode as described in "2.3.5 Operation mode control circuit".
Note: No hardware function is available for external direct monitoring of the basic clock. The oscillation fre-
quency can be adjusted by programming the system to output pulses at a certain frequency to a port
(for example, a clock output) with interrupts disabled and the watchdog timer disabled and monitoring
the output. An adjustment program must be created in advance for a system that requires adjustment of
the oscillation frequency.
To prevent the dead lock of the CPU core due to the software-controlled enabling/disabling of the oscil-
lation, an internal factor reset is generated depending on the combination of values of the clock selected as
the main system clock, SYSCR2<XEN>, SYSCR2<XTEN> and the P0 port function control register
P0FC0.
Note: It takes a certain period of time after SYSCR2<SYSCK> is changed before the main system clock is
switched. If the currently operating oscillation circuit is stopped before the main system clock is
switched, the internal condition becomes as shown in Table 2-1 and a system clock reset occurs. For
details of clock switching, refer to "2.3.6 Operation Mode Control".
Figure 2-4 Examples of Oscillator Connection
2.3.3.2 Clock gear
The clock gear is a circuit that selects a gear clock (fcgck) obtained by dividing the high-frequency
clock (fc) and inputs it to the timing generator.
Selects a divided clock at CGCR<FCGCKSEL>.
Two machine cycles are needed after CGCR<FCGCKSEL> is changed before the gear clock (fcgck) is
changed.
The gear clock (fcgck) may be longer than the set clock width, immediately after CGCR<FCGCKSEL>
is changed.
Table 2-1 Prohibited Combinations of Oscillation Enable Register Conditions
P0FC0
SYSCR2
<XEN>
SYSCR2
<XTEN>
SYSCR2
<SYSCK>
State
Don't Care 0 0 Don’t Care All the oscillation circuits are stopped.
Don’t Care Don’t Care 0 1
The low-frequency clock (fs) is selected as the main system
clock, but the low-frequency clock oscillation circuit is
stopped.
Don’t Care 0 Don’t Care 0
The high-frequency clock (fc) is selected as the main system
clock, but the high-frequency clock oscillation circuit is
stopped.
0 1 Don’t Care Don’t Care
The high-frequency clock oscillation circuit is allowed to
oscillate, but the port is set as a general-purpose port.
XIN
High-frequency clock
XOUT
(a) Crystal or ceramic
oscillator
XIN XOUT
(b) External oscillator
(Open)
XTIN
Low-frequency clock
XTOUT
(c) Crystal oscillator
XTIN XTOUT
(d) External oscillator
(Open)