Toshiba DP120F, Руководство по обслуживанию

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March 2000 © TOSHIBA TEC 7-53 DP120F/DP125F Circuit Description
Pin Function Table
• CPU Signal Table
No. Signal Name Type Functions
1 RWX O Read/write signal (H: Read, L: Write)
Requests each IC to read or write data.
2 DTACKX I Data transfer acknowledge (active-low)
The DMAC GA (IC16) indicates the end of data trans-
fer.
3 BGX O Bus ground (active-low)
Indicates the release of the bus to the DMAC GA.
4 BRX I Bus request (active-low)
The DMAC GA makes a request for bus control.
5,41 +5V - +5V
6 CPUCK I CPU operation clock (16MHz)
7, 23, 56 SG - Signal ground
8 MODE - +5V
9 HALTX O Halt signal (active-low)
Indicates that the CPU (IC66) is stopped.
10 RESETX I Reset signal (active-low)
Resets the system.
11 AVECX - +5V
12 BERR - +5V
13-15 IPL2-0X I Interrupt request 0-2 signals (active-low)
The DMAC GA makes requests for interrupt process-
ing.
16-18 FC2-0 O CPU operating status 0-2 signals
Indicate the operating status of the CPU to the DMAC
GA.
19 A0 - Unused
20-22, 24-40, A1-23 O Address bus
42-44
45-55, 57-61 D0-15 I/O Data bus
62 ASX O Address strobe signal (active-low)
Causes the address bus data to be latched.
63 UDSX O Upper data strobe signal (active-low)
Causes the upper data bus data to be latched.
64 LDSX O Lower data strobe signal (active-low)
Causes the lower data bus data to be latched.
I: Input O: Output I/O: Bidirectional