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THCV235-Q_THCV236-Q_Rev.3.40_E

2016 THine Electronics, Inc.

THine Electronics, Inc.

49/68

Security E

Table 45.

THCV236-Q Main-Link Control Register Map

Address (Hex)

Bit# R/W

Default

(Hex)

Name

Description

Note

Sub-Link

Master

Sub-Link

Slave

0x50 0xD0

7 RW (*1)

MAINMODE

MAINMODE setting
0: V-by-One

HS Mode

1: Sync Free Mode

6 RW (*1)

HFSEL

HFSEL setting
0: High Frequency Mode Disable
1: High Frequency Mode Enable

5 RW 0 COL1

COL1 setting
when MAINMODE =0
0: Color Space Converter Disable
1: Color Space Converter Enable
when MAINMODE =1
Data Width Setting. See Table 20.

4 RW (*1)

COL0

COL0 setting
Data Width Setting. See Table 20.

3 RW 0

Reserved

2:1 RW 0x0

Reserved

0 RW 0 TTLDRV

TTLDRV setting
0: Weak Drive Strength
1: Normal Drive Strength

0x51 0xD1

7:6

R 0x0

Reserved

5 RW 0 SSEN

SSEN setting
0: SSCG Disable
1: SSCG Enable

(*2)

4:0 RW 0x05 SPREAD

SSCG modulation depth setting
Spread depth = ±SPREAD x 0.1% (Center Spread)

0x52 0xD2

7:4

R 0x0

Reserved

3:0

0xD

FMOD

SSCG Modulation Frequency setting

0x53 0xD3 7:2 R 0x00

Reserved

1 RW 0

Reserved

0 RW 0 BET_SEL

Main-Link / Sub-Link Field BET Mode select
0: Main-Link Field BET Mode
1: Sub-Link Field BET Mode

0x54 0xD4 7

R 0

Reserved

6:0

0x3E

Reserved. Must be default setting.

0x55

-0x6C

0xD5

-0xEC

7:0 RW 0x00

Reserved

0x6D 0xED

7:3

0x00

Reserved

2 RW 0 OUTSEL_ENABLE

Permanent Clock Output Enable setting
0: Permanent Clock Output Disable
1: Permanent Clock Output Enable

1:0 RW 0x1 OUTSEL_SETTING

Permanent Clock Frequency setting
00: 80MHz (Clock Period : t

OSC

)

01: 40MHz (Clock Period : t

OSC

/2)

10: 20MHz (Clock Period : t

OSC

/4)

11: 10MHz (Clock Period : t

OSC

/8)

(*3)

0x6E 0xEE

7:1

0x00

Reserved

Reserved. Must be 1

0x6F 0xEF 7:0 R 0x00

Reserved

0x70 0xF0

7:2

0x00

Reserved

Reserved. Must be 0

0 RW 0 PLL_SET_EN

SSCG PLL setting register Enable
1: Enable
0: Disable

0x71

-0x75

0xF1

-0xF5

7:0 R 0x00

Reserved

0x76 0xF6

7:6

0x0

Reserved

5:0

0xXX

PLL_SET0

SSCG PLL setting

(*4)

0x77 0xF7

7:4

0x0

Reserved

3:0

0x0

Reserved. Must be default setting.

0x78

0xF8

7:0

0xXX

PLL_SET1

SSCG PLL setting

(*4)

0x79

-0x7B

0xF9

-0xFB

7:0

0x00

Reserved. Must be default setting.

0x7C 0xFC

7:6

R 0x0

Reserved.

5:0

0xXX

PLL_SET2

SSCG PLL setting

(*4)

0x7D

-0x7F

0xFD

-0xFF

7:0

0xXX

Reserved. Must be default setting.

Default value depends on RXDEFSEL setting when Power on sequence. RXDEFSEL=1

→

default value is 0, RXDEFSEL=0

→

default value is 1.

SSEN=1 and SPREAD=0 setting is forbidden.

Described value is typical value. It has variation in the range from min spec value to max spec value of t

OSC

See Table 11, Table 21.

Содержание CEL SerDes THCV235-Q

Страница 1: ...color space conversion function Wide frequency range AC coupling for high speed lanes CDR requires no external frequency reference Wide range supply voltage from 1 7V to 3 6V Additional spread spectr...

Страница 2: ...35 Q only 14 Permanent Clock Output THCV236 Q only 15 Spread Spectrum Clock Generator SSCG 15 Data Enable 17 Hot Plug Function 18 Lock Detect Function 18 Field BET Operation 20 Data Width and Frequenc...

Страница 3: ...right 2016 THine Electronics Inc THine Electronics Inc 3 68 Security E Electrical Specification 50 AC Timing Diagrams and Test Circuits 56 PCB Layout Guideline regarding VDD and AVDD for THCV236 Q 66...

Страница 4: ...NC VDD 56 55 54 53 CAPOUT LOCKN MSSEL HTPDN SUBMODE D0 60 59 58 57 MAINMODE RCMN CAPINA RXP RXN 64 63 62 61 BET OE HFSEL RCMP 16 48 TOP VIEW 65 EXPGND D13 RXDEFSEL THCV235 Q QFN 64pin PDN0 D4 1 PDN1 2...

Страница 5: ...lock Stretching mode 1 Low Speed Data Bridge Mode Forbid the different setting between THCV235 Q and THCV236 Q LOCKN MSSEL 63 IL LOCKN Lock Detect Input when PDN1 0 MSSEL Sub Link Master Slave Select...

Страница 6: ...Input Output when PDN1 1 When SUBMODE 0 SD1 is used as SCL input output for 2 wire serial I F requires pull up resistor to VDD When SUBMODE 1 and MSSEL 0 SD1 is input When SUBMODE 1 and MSSEL 1 SD1 is...

Страница 7: ...e 19 0 Falling Edge 1 Rising Edge BETOUT Field BET Result Output when Field BET mode LFSEL 3 I Low Frequency mode select 0 Low Frequency mode Disable 1 Low Frequency mode Enable PDN1 2 IL Sub Link Pow...

Страница 8: ...CMLDRV SD2 AIN0 GPIO3 CMLDRV SD2 input SD2 output 6 AIN0 GPIO3 5 LATEN SD3 AIN1 GPIO4 1 SD3 output 6 SD3 input AIN1 GPIO4 5 LATEN 3 SSEN GPIO0 SSEN SSEN SSEN GPIO0 4 GPIO0 4 BET GPIO1 BET BET BET GPIO...

Страница 9: ...1 Low Speed Data Bridge Mode Forbid the different setting between THCV235 Q and THCV236 Q LOCKN MSSEL 55 BO LOCKN Lock Detect Output when PDN1 0 Must be connected to Tx LOCKN with 10k pull up resisto...

Страница 10: ...input output for 2 wire serial I F requires pull up resistor to VDD When SUBMODE 1 and MSSEL 0 SD1 is input When SUBMODE 1 and MSSEL 1 SD1 is output COL1 SD0 8 B COL1 Color Space Converter Enable whe...

Страница 11: ...6 B RF Output Clock Triggering edge select See Figure 20 0 Falling Edge 1 Rising Edge BETOUT Field BET Result Output RXDEFSEL 62 I Internal Register Default Setting Select See Table 44 Table 45 0 for...

Страница 12: ...tput 6 SD1 SCL SD1 SCL SD1 SCL TTLDRV SD2 AIN0 GPIO1 TTLDRV SD2 input SD2 output 6 AIN0 AIN0 GPIO1 4 LATEN SD3 AIN1 GPIO0 1 SD3 output 6 SD3 input AIN1 AIN1 GPIO0 4 LATEN 3 D24 GPIO3 D24 D24 D24 D24 G...

Страница 13: ...wire serial interface or GPIOs They also can report interrupt events caused by change of GPIO inputs and internal statuses Functional Description Internal Reference Output Input Function CAPOUT CAPIN...

Страница 14: ...1 1 setting COL1 is external pin when PDN1 0 or internal register when PDN1 1 Color space conversion coefficients are compliant with ITU R BT 709 5 Pre emphasis and Drive Select Function THCV235 Q onl...

Страница 15: ...01 40MHz default 10 20MHz 11 10MHz 1 typical value Spread Spectrum Clock Generator SSCG The THCV235 Q serial data output and the THCV236 Q parallel data and clock outputs are modulated by programmable...

Страница 16: ...EX Description Sub Link Master side Sub Link Slave side Case1 Case2 Case3 THCV235 Q THCV236 Q 1 0x70 0xF0 0x01 Set 1 to PLL_SET_EN 2 0x76 0xF6 0x02 0x02 0x01 Set PLL_SET0 3 0x78 0xF8 0x3C 0x30 0x20 Se...

Страница 17: ...of the Basic Operation of the Chipset in V by One HS mode There are some requirements for DE Figure 3 shows the timing diagram of it Note In V by One HS Mode MAINMODE 0 and High Frequency Mode HFSEL...

Страница 18: ...iver can be omitted as an application option In this case HTPDN at the Transmitter side should always be taken as low When PDN1 1 Sub Link Active HTPDN is transferred to Transmitter via Sub Link line...

Страница 19: ...Inc 19 68 Security E Table 15 HTPDN LOCKN transmission route setting PDN1 HTPDN LOCKN 0 HTPDN LOCKN are transmitted via external DC signal 1 HTPDN LOCKN are transmitted via Sub Link Figure 4 Hot plug...

Страница 20: ...ice The BETOUT pin goes LOW whenever bit errors occur or it stays HIGH when there is no bit error In Main Link Field BET mode user can select two kinds of check result latched result or NOT latched re...

Страница 21: ...BET Operation Latched Result 1 1 5 0 0 1 2 1 4 0 1 1 5 1 1 5 0 1 Pin setting Note that BET pin should be 0 at power on sequence 2 THCV235 Q Register setting 0x53 bit1 THCV236 Q Pin setting Note that...

Страница 22: ...0 50 70 50 70 x25 20 3 2 70 160 70 160 0 1 0 0 1 50 70 50 70 x20 16 3 2 70 160 70 160 0 1 0 1 0 50 70 50 70 x25 30 3 Color Space Conversion 2 70 160 70 160 Color Space Conversion 0 1 0 1 1 50 70 50 70...

Страница 23: ...0 0 7 5 15 16 4 32 5 x80 32 3 0 0 1 0 1 10 20 19 2 38 x60 24 3 0 0 1 1 0 7 5 15 16 4 32 5 x80 32 3 Color Space Conversion 0 0 1 1 1 10 20 19 2 38 x60 24 3 Color Space Conversion 0 1 0 0 0 70 160 100 1...

Страница 24: ...G8 G6 Y8 Y6 G8 G6 D15 G9 G7 G9 G7 G9 G7 G9 G7 Y9 Y7 G9 G7 D16 B2 1 B0 1 B2 1 B0 1 B2 1 B0 1 B2 1 B0 1 B2 B0 D17 B3 1 B1 1 B3 1 B1 1 B3 1 B1 1 B3 1 B1 1 B3 B1 D18 B4 1 B2 1 B4 1 B2 1 B4 1 B2 1 B4 1 B2...

Страница 25: ...D7 YC7 D8 D8 D8 D8 D8 D8 D8 D8 Y0 D8 RAW0 D9 D9 D9 D9 D9 D9 D9 D9 Y1 D9 RAW1 D10 D10 D10 D10 D10 D10 D10 D10 Y2 D10 RAW2 D11 D11 D11 D11 D11 D11 D11 D11 Y3 D11 RAW3 D12 D12 D12 D12 D12 D12 D12 D12 Y4...

Страница 26: ...wire serial I F Sub Link Master 2 wire serial Slave 1 Sub Link Slave 2 wire serial Master 1 0 Low Speed Data Bridge Sub Link Master 1 Sub Link Slave 2 wire serial I F Mode 2 wire serial I F Mode enab...

Страница 27: ...ccess or remote side 2 wire serial access 2WIRE_MODE Sub Link Master side register 0x0F bit1 0 selects whether 2 wire serial slave of Sub Link Master perform clock stretching When 2WIRE_MODE 00 Sub Li...

Страница 28: ...n directly access Sub Link Master s register by 2 wire serial I F Register address of Sub Link Master is from 0x00 to 0x7F See Register Map for more information Figure 9 Host to Sub Link Master Regist...

Страница 29: ...ce Value corresponding to AIN1 and AIN0 setting e g AIN1 AIN0 0 0 7 h0B W 0x20 4 Set the byte number written to Sub Link Slave Max 16byte Byte number register value 1 W 0x21 5 Set the start address of...

Страница 30: ...x26 1 6 2 2 wire serial slave of Sub Link Master perform clock stretching until Sub Link Slave register access is completed When read access is completed SCL is released and read data is stored in Sub...

Страница 31: ...the data for remote side 2 wire serial slave to write Max 16byte W 0x10 0x1F 4 Set slave address of access target 2 wire serial slave choose the value set in 0x04 0x0B 6 0 and set 0 to 0x20 bit7 W 0x...

Страница 32: ...value 1 W 0x21 6 Set the low order bits 7 0 of start address of remote side 2 wire serial slave register to write W 0x27 7 Set the high order bits 15 8 of start address of remote side 2 wire serial s...

Страница 33: ...0x24 6 Write 1 to RD_START_8B Start read access to remote side 2 wire serial slave register W 0x26 1 7 2 2 wire serial slave of Sub Link Master perform clock stretching until Sub Link Slave register a...

Страница 34: ...emote side 2 wire serial slave register to read W 0x2A 7 Write 1 to RD_START_16B Start read access to remote side 2 wire serial slave register W 0x2C 1 8 2 2 wire serial slave of Sub Link Master perfo...

Страница 35: ...ns Through GPIO is available by only GPIO4 and GPIO3 pin See Through GPIO section and Programmable GPIO section about detail of respective GPIO type Table 33 GPIO Type GPIO GPIO Type Through GPIO Prog...

Страница 36: ...1 GPIO_INPUT_MONITOR Each GPIO output signal goes to Low when Sub Link communication fails Sub Link communication status can be observed by register read 0x82 bit2 COMERR_INT When the THCV236 Q is Sub...

Страница 37: ...put Configuration I Input O Output Unavailable Register Settings GPIO Type GPIO IO Direction Input Output GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 Address HEX Value BIN Address HEX Value BIN Master 2 0 I I 0x40...

Страница 38: ...wire serial interface the THCV235 Q and THCV236 Q can monitor any changes of GPIO input pins Sub Link communication statuses and internal statuses as an interrupt About the way to make interruption o...

Страница 39: ...ster device is output respectively from SD2 SD1 and SD0 of Sub Link Slave device by LVCMOS push pull output buffer Low speed data input to SD3 of Sub Link Slave device is output from SD3 of Sub Link M...

Страница 40: ...THCV236 Q have two types of register address map depending upon Sub Link configuration Sub Link Master 2 wire serial slave is connected to external HOST MPU 2 wire serial master Sub Link Slave 2 wire...

Страница 41: ...T Cause of interrupt Sub Link communication Error 0 No communication error on Sub Link ever 1 Communication error on Sub Link once happened Any write action clear this bit into 0 1 RW 0 2WIRE_TIMEOUT_...

Страница 42: ...6 2 wire serial I F Write Read Data 6 0x17 7 0 RW 0x00 2WIRE_DATA7 2 wire serial I F Write Read Data 7 0x18 7 0 RW 0x00 2WIRE_DATA8 2 wire serial I F Write Read Data 8 0x19 7 0 RW 0x00 2WIRE_DATA9 2 w...

Страница 43: ...time out Any write action clear this bit into 0 0 RW 0 SLINK_TIMEOUT_INT Cause of interrupt Sub Link time out0 Sub Link access in time ever 1 Sub Link has once had time out Any write action clear this...

Страница 44: ...put value 0 R 0 GPIO0_INPUT_MONITOR GPIO0 input value 0x42 0xC2 7 5 R 0x0 Reserved 4 RW 0 GPIO4_OUT GPIO4 output value setting 2 3 RW 0 GPIO3_OUT GPIO3 output value setting 2 RW 0 GPIO2_OUT GPIO2 outp...

Страница 45: ...RW 1 GPIO0_INT_ENABLE GPIO0 interrupt enable 0 Disable 1 Enable 0x46 0xC6 7 5 R 0x0 Reserved 4 RW 0 GPIO4_OUTBUF_SEL GPIO4 output buffer select 0 GPIO4 is open drain output 1 GPIO4 is push pull output...

Страница 46: ...2 0xD2 7 4 R 0x0 Reserved 3 0 RW 0xD FMOD SSCG Modulation Frequency setting 0x53 0xD3 7 2 R 0x00 Reserved 1 RW 0 BET Field BET Mode Enable setting 0 Normal Mode 1 Field BET Operation 0 RW 0 BET_SEL Ma...

Страница 47: ...ue setting 2 RW 0 GPIO2_OUT GPIO2 output value setting 1 RW 0 GPIO1_OUT GPIO1 output value setting 0 RW 0 GPIO0_OUT GPIO0 output value setting 0x43 0xC3 7 5 R 0x0 Reserved 4 RW 4 GPIO_IO_SEL GPIO inpu...

Страница 48: ...nable 0 Disable 1 Enable 0x46 0xC6 7 5 R 0x0 Reserved 4 RW 0 GPIO4_OUTBUF_SEL GPIO4 output buffer select 0 GPIO4 is open drain output 1 GPIO4 is push pull output 3 RW 0 GPIO3_OUTBUF_SEL GPIO3 output b...

Страница 49: ...0 RW 0x3E Reserved Must be default setting 0x55 0x6C 0xD5 0xEC 7 0 RW 0x00 Reserved 0x6D 0xED 7 3 R 0x00 Reserved 2 RW 0 OUTSEL_ENABLE Permanent Clock Output Enable setting 0 Permanent Clock Output Di...

Страница 50: ...issipation 25 C 2 5 W Recommended Operating Conditions Table 47 Recommended Operating Condition Parameter Min Typ Max Unit Supply Voltage VDD AVDD 1 7 3 6 V Operating Temperature 40 105 C Electrical S...

Страница 51: ...L DC Specification THCV236 Q Symbol Parameter Condition Min Typ Max Unit VRTH CML Differential Input High Threshold 50 mV VRTL CML Differential Input High Threshold 50 mV IRIH CML Input Leak Current H...

Страница 52: ...teristics THCV235 Q Symbol Parameter Condition Min Typ Max Unit tTRF CML Output Rise and Fall Time 20 80 50 150 ps tTCIP CLKIN Period See Table 20 1000 Freq Range MHz ns tTCH CLKIN High Time 0 35 tTCI...

Страница 53: ...ow to LOCKN High Delay 10 us tRLCK0 LOCKN Low to Data Output Delay 5 ms tRLCK1 LOCKN High to Data Output Stop Delay 10 us tROSC0 PDN0 High to Permanent Clock output Delay OUTSEL 1 5 ms tROSC1 LOCKN Lo...

Страница 54: ...ust be suppressed by the input filter 50 ns tPDS Required wait time from PDN1 high to START condition 2 ms 1 Please adjust Pull up resistor and bus capacitance to meet the spec value Table 58 2 wire s...

Страница 55: ...pending on characteristics of 2 wire serial slave devices connected to Sub Link Slave us Table 60 Sub Link control switching characteristics 2 wire serial I F Mode Symbol Parameter Min Typ Max Unit tP...

Страница 56: ...E AC Timing Diagrams and Test Circuits LVCMOS Input Output Switching Characteristics tTS tTH tTCH RF 1 tTCL RF 0 tTCIP RF 0 RF 1 VDD 2 VDD 2 VDD 2 CLKIN D31 D0 HSYNC VSYNC DE VDD 2 VDD 2 tTCL RF 1 tTC...

Страница 57: ...36 Q_Rev 3 40_E Copyright 2016 THine Electronics Inc THine Electronics Inc 57 68 Security E CML Output Switching Characteristics Figure 21 CML Output Switching Characteristics Figure 22 CML Buffer Equ...

Страница 58: ...yright 2016 THine Electronics Inc THine Electronics Inc 58 68 Security E CML Bi directional Output Test Circuit Figure 23 Bi directional CML VBOD VBOC Test Circuit Figure 24 Bi directional CML Switchi...

Страница 59: ...THCV235 Q_THCV236 Q_Rev 3 40_E Copyright 2016 THine Electronics Inc THine Electronics Inc 59 68 Security E Latency Characteristics Figure 25 THCV235 Q Latency Figure 26 THCV236 Q Latency...

Страница 60: ...Q_THCV236 Q_Rev 3 40_E Copyright 2016 THine Electronics Inc THine Electronics Inc 60 68 Security E Lock and Unlock Sequence Figure 27 THCV235 Q Lock Unlock Sequence Figure 28 THCV236 Q Lock Unlock Se...

Страница 61: ...nc THine Electronics Inc 61 68 Security E 2 wire serial I F Switching Characteristics Figure 29 2 wire serial interface Timing Diagram Figure 30 Write access completion time to Sub Link Slave register...

Страница 62: ...ight 2016 THine Electronics Inc THine Electronics Inc 62 68 Security E Figure 32 Write access completion time to Remote side 2 wire serial slave register Figure 33 Read access completion time to Remot...

Страница 63: ...Figure 34 Through GPIO delay Read data of 0x41 Data_A A GPIO Input port GPIO4 GPIO0 tPH SD0 SDA Read data of 0x41 Data_B A Data_A Data_B tPS Figure 35 Programmable GPIO input timing at Sub Link Maste...

Страница 64: ...68 Security E Figure 38 GPIO input and other interrupt event timing at Sub Link Master side Figure 39 GPIO input and other interrupt event timing at Sub Link Slave side Clock Stretching Mode Figure 39...

Страница 65: ...HCV235 Q_THCV236 Q_Rev 3 40_E Copyright 2016 THine Electronics Inc THine Electronics Inc 65 68 Security E Low Speed Data Bridge Switching Characteristics Figure 40 Low Speed Data Bridge Mode Data Dela...

Страница 66: ...rse side layer to AVDD please place ferrite bead between through hole and AVDD VDD pins Good Example1 2 If it is needed to set ferrite beads on reverse side please set GND through hole between AVDD an...

Страница 68: ...t is specified as a product conforming to the demands and specifications of ISO TS16949 the Specified Product in this data sheet THine Electronics Inc THine accepts no liability whatsoever for any pro...

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