THCV235-Q_THCV236-Q_Rev.3.40_E
Copyright
©
2016 THine Electronics, Inc.
THine Electronics, Inc.
54/68
Security E
Table 57.
2-wire serial slave AC Timing (Sub-Link Master device)
Symbol
Parameter
Min
Typ Max Unit
f
SCL
SCL clock frequency
-
-
400
kHz
t
HD;STA
Hold time (repeated) START condition
0.6
-
-
us
t
LOW
LOW period of the SCL clock
1.3
-
-
us
t
HIGH
HIGH period of the SCL clock
0.6
-
-
us
t
HD;DAT
Data hold time: output
-
9×t
OSC
- us
Data hold time: input
20
-
-
ns
t
SU;DAT
Data setup time: output
500
-
-
ns
Data setup time: input
100
-
-
ns
t
r
Rise time of both SDA and SCL signals
-
-
300
(*1)
ns
t
f
Fall time of both SDA and SCL signals
(pull-up resistor:2.5k
Ω
,bus capacitance:400pF)
- -
300
ns
t
SU;STO
Setup time for STOP condition
0.6
-
-
ns
t
BUF
Bus free time between a STOP and START condition
1.3
-
-
us
t
SP
Pulse width of spikes which must be suppressed by the input filter
-
-
50
ns
t
PDS
Required wait time from PDN1 high to START condition
2
-
-
ms
*1 Please adjust Pull-up resistor and bus capacitance to meet the spec value.
Table 58.
2-wire serial master AC Timing (Sub-Link Slave device)
Symbol
Parameter
Min
Typ
Max
Unit
t
OSC
Cycle of internal oscillator clock
10.417
12.5
15.625
ns
t
HD;STA
Hold time (repeated) START condition
-
(SCL_W_H × 8 – 3)
× t
OSC
- us
t
LOW
LOW period of the SCL clock
-
((S 1) × 8 + 8)
× t
OSC
- us
t
HIGH
HIGH period of the SCL clock
-
((S 1) × 8 + 8)
× t
OSC
- us
t
HD;DAT
Data hold time: output
-
9×t
OSC
-
us
Data hold time: input
20
-
-
ns
t
SU;DAT
Data setup time: output
31×t
OSC
- -
ns
Data setup time: input
100
-
-
ns
t
r
Rise time of both SDA and SCL signals
-
-
300(*1)
ns
t
f
Fall time of both SDA and SCL signals
(pull-up resistor:2.5k
Ω
,bus capacitance:400pF)
- -
300
ns
t
SU;STO
Setup time for STOP condition
-
386×t
OSC
-
ns
t
BUF
Bus free time between a STOP and START
condition
4.7
-
-
us
*1 Please adjust Pull-up resistor and bus capacitance to meet the spec value.
