THCV235-Q_THCV236-Q_Rev.3.40_E
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©
2016 THine Electronics, Inc.
THine Electronics, Inc.
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Security E
Data Enable
Figure 2 is the conceptual diagram of the V-by-One
®
HS mode operation (MAINMODE=0) of the chipset.
Figure 2.
Conceptual Diagram of the Basic Operation of the Chipset in V-by-One
®
HS mode
There are some requirements for DE. Figure 3 shows the timing diagram of it.
Note: In V-by-One
®
HS Mode (MAINMODE=0) and High Frequency Mode (HFSEL=1), the period between rising edges of DE (tDEINT),
high time of DE (tDEH) should always satisfy following equations.
tDEH = tTCIP*(2m)
tDEINT = tTCIP*(2n)
m,n=2,3,4,5,6……
Figure 3.
Data and Synchronizing Signals Transmission Timing Diagram in V-by-One
®
HS mode
