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SLOS743L – AUGUST 2011 – REVISED MARCH 2017
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Detailed Description
Copyright © 2011–2017, Texas Instruments Incorporated
6.8
Transmitter – Digital Section
The digital part of the transmitter is a mirror of the receiver. The settings controlled the ISO Control
register (0x01) are applied to the transmitter just like the receiver. In the TRF7970A default mode the
TRF7970A automatically adds these special signals: start of communication, end of communication, SOF,
EOF, parity bits, and CRC bytes.
The data is then coded to modulation pulse levels and sent to the RF output stage modulation control unit.
Similar to working with the receiver, this means that the external system MCU must only load the FIFO
with data, and all the microcoding is done automatically, again saving the firmware developer code space
and time. Additionally, all of the registers used for transmit parameter control are automatically preset to
optimum values when a new selection is entered into the ISO Control register (0x01).
NOTE
The FIFO must be reset before starting any transmission with direct command 0x0F.
There are two ways to start the transmit operation:
•
Send the transmit command and the number of bytes to be transmitted first, and then start to send the
data to the FIFO. The transmission starts when first data byte is written into the FIFO.
•
Load the number of bytes to be sent into registers 0x1D and 0x1E and load the data to be sent into the
FIFO (address 0x1F), followed by sending a transmit command (see Direct Commands section). The
transmission then starts when the transmit command is received.
NOTE
If the data length is longer than the FIFO, the TRF7970A notifies the external system MCU
when most of the data from the FIFO has been transmitted by sending an interrupt request
with a flag in the IRQ register to indicate a FIFO low or high status. The external system
should respond by loading the next data packet into the FIFO.
At the end of a transmit operation, the external system MCU is notified by interrupt request (IRQ) with a
flag in IRQ register (0x0C) indicating TX is complete (example value = 0x80).
The TX Length registers also support incomplete byte transmission. The high two nibbles in register 0x1D
and the nibble composed of bits B4 through B7 in register 0x1E store the number of complete bytes to be
transmitted. Bit B0 in register 0x1E is a flag indicating that there are also additional bits to be transmitted
that do not form a complete byte. The number of bits is stored in bits B1 through B3 of the same register
(0x1E).
Some protocols have options, and there are two sublevel configuration registers to select the TX protocol
options.
•
ISO/IEC 14443 B TX Options register (0x02). This register controls the SOF and EOF selection and
EGT selection for the ISO/IEC 14443 B protocol.
•
ISO/IEC 14443 A High Bit Rate Options and Parity register (0x03). This register enables the use of
different bit rates for RX and TX operations in the ISO/IEC 14443 high bit rate protocol and also
selects the parity method in the ISO/IEC 14443 A high bit rate protocol.
The digital section also has a timer. The timer can be used to start the transmit operation at a specified
time in accordance with a selected event.
