12
SLOS743L – AUGUST 2011 – REVISED MARCH 2017
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Specifications
Copyright © 2011–2017, Texas Instruments Incorporated
(1)
This data was taken using the JEDEC standard high-K test PCB.
(2)
Power rating is determined with a junction temperature of 125°C. This is the temperature at which distortion starts to increase
substantially. Thermal management of the final PCB should strive to keep the junction temperature at or below 125°C for best
performance and long-term reliability.
5.5
Thermal Resistance Characteristics
PACKAGE
θ
JC
θ
JA
(1)
POWER RATING
(2)
T
A
≤
25°C
T
A
≤
85°C
RHB (32 pin)
31°C/W
36.4°C/W
2.7 W
1.1 W
(1)
TI recommends a DATA_CLK speed of 2 MHz. Higher data clock depends on the capacitive load. Maximum SPI clock speed should not
exceed 10 MHz. This clock speed is acceptable only when external capacitive load is less than 30 pF. MISO driver has a typical output
resistance of 400
Ω
(12-ns time constant when 30-pF load used).
5.6
Switching Characteristics
TYP operating conditions are T
A
= 25°C, VIN = 5 V, full-power mode (unless otherwise noted)
MIN and MAX operating conditions are over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
t
LO/HI
DATA_CLK time high or low, one half of DATA_CLK at
50% duty cycle
Depends on capacitive load on the
I/O lines
(1)
250
62.5
50
ns
t
STE,LEAD
Slave select lead time, slave select low to clock
200
ns
t
STE,LAG
Slave select lag time, last clock to slave select high
200
ns
t
STE,DIS
Slave select disable time, slave select rising edge to
next slave select falling edge
300
ns
t
SU,SI
MOSI input data setup time
15
ns
t
HD,SI
MOSI input data hold time
15
ns
t
SU,SO
MISO input data setup time
15
ns
t
HD,SO
MISO input data hold time
15
ns
t
VALID,SO
MISO output data valid time
DATA_CLK edge to MISO valid,
C
L
≤
30 pF
30
50
75
ns
