Multicore Fixed and Floating-Point System-on-Chip
Copyright 2012 Texas Instruments Incorporated
Device Overview
35
SPRS689D—March 2012
TMS320C6670
2.4.2.7 HyperLink Boot Device Configuration
2.4.3 PLL Settings
The PLL default settings are determined by the BOOTMODE[12:10] bits.
shows settings for various
input clock frequencies. This will set the PLL to the maximum clock setting for the device.
CLK = CLKIN × (PLLM+1) ÷ (2 × (PLLD+1))
The configuration for the PASS PLL is also shown. The PASS PLL is configured with these values only if the Ethernet
boot mode is selected with the input clock set to match the main PLL clock (not the SGMII SerDes clock). See
for details on configuring Ethernet boot mode. The output from the PASS PLL goes through an on-chip
divider to reduce the operating frequency before reaching the NETCP. The PASS PLL generates 1050 MHz, and after
the chip divider (/3), applies 350 MHz to the NETCP.
The Main PLL is controlled using a PLL controller and a chip-level MMR. The DDR3 PLL and PASS PLL are
controlled by chip level MMRs. For details on how to set up the PLL see Section 7.5
on page 128. For details on the operation of the PLL controller module, see the
Phase Locked Loop (PLL)
Controller for KeyStone Devices User Guide
in
2.9 ‘‘Related Documentation from Texas Instruments’’ on page 66
Figure 2-10
HyperLink Boot Device Configuration Fields
9
8
7
6
5
4
3
Reserved
Data Rate
Ref Clock
Reserved
Table 2-12
HyperLink Boot Device Configuration Field Descriptions
Bit
Field
Description
9
Reserved
Reserved
8-7
Data Rate
HyperLink data rate configuration
0 = 1.25 GBs
1 = 3.125 GBs
2 = 6.25 GBs
3 = Reserved
6-5
Ref Clocks
HyperLink reference clock configuration
0 = 156.25 MHz
1 = 250 MHz
2 = 312.5 MHz
3 = Reserved
4-3
Reserved
Reserved
End of Table 2-12
Table 2-13
C66x CorePac System PLL Configuration
BOOTMODE
[12:10]
Input Clock
Freq (MHz)
800 MHz Device
1000 MHz Device
1200 MHz Device
PA = 350 MHz
(1)
1 The PASS PLL generates 1050 MHz and is internally divided by 3 to feed 350 MHz to the packet accelerator.
PLLD
PLLM
DSP ƒ
PLLD
PLLM
DSP ƒ
PLLD
PLLM
DSP ƒ
PLLD
PLLM
DSP ƒ
(2)
2 ƒ represents frequency in MHz.
0b000
50.00
0 31 800
0 39 1000
0 47 1200
0 41 1050
0b001
66.67
0 23 800.04
0 29 1000.05
0 35 1200.06
1 62 1050.053
0b010
80.00
0 19 800
0 24 1000
0 29 1200
3 104
1050
0b011
100.00 0 15 800
0 19 1000
0 23 1200
0 20 1050
0b100
156.25
24 255 800
4 63 1000
24 383 1200
24 335 1050
0b101
250.00 4 31 800
0 7 1000
4 47 1200
4 41 1050
0b110
312.50
24 127 800
4 31 1000
24 191 1200
24 167 1050
0b111
122.88
47 624 800
28 471 999.989
31 624 1200
11 204 1049.6
Содержание TMS320C6670
Страница 225: ......