Multicore Fixed and Floating-Point System-on-Chip
Copyright 2012 Texas Instruments Incorporated
TMS320C6670 Peripheral Information and Electrical Specifications
123
SPRS689D—March 2012
TMS320C6670
The following sequence must be followed during a power-on reset:
1.
Wait for all power supplies to reach normal operating conditions while keeping the POR pin asserted (driven
low). While POR is asserted, all pins except RESETSTAT will be set to high-impedance. After the POR pin is
de-asserted (driven high), all Z group pins, low group pins, and high group pins are set to their reset state and
will remain at their reset state until otherwise configured by their respective peripheral. All peripherals that are
power managed, are disabled after a power-on reset and must be enabled through the Device State Control
Registers (for more details, see Section Table 3-2
‘‘Device State Control Registers’’
2.
Clocks are reset, and they are propagated throughout the chip to reset any logic that was using reset
synchronously. All logic is now reset and RESETSTAT will be driven low, indicating that the device is in reset.
3.
POR must be held active until all supplies on the board are stable, and then for at least an additional period of
time (as specified in Section 7.2.1
on page 110) for the chip-level PLLs to lock.
4.
The POR pin can now be de-asserted. Reset-sampled pin values are latched at this point. Then all chip-level
PLLs are taken out of reset, they begin their locking sequence, and all power-on device initialization processes
begin.
5.
After device initialization is complete, the RESETSTAT pin is de-asserted (driven high). By this time, the
DDR3 PLL has already completed its locking sequence and is supplying a valid clock. The system clocks of both
PLL controllers are allowed to finish their current cycles and then paused for 10 cycles of their respective
system reference clocks. After the pause, the system clocks are restarted at their default divide by settings.
6.
The device is now out of reset and device execution begins as dictated by the selected boot mode.
Note—
To most of the device, reset is de-asserted only when the POR and RESET pins are both de-asserted
(driven high). Therefore, in the sequence described above, if the RESET pin is held low past the low period
of the POR pin, most of the device will remain in reset. The RESET pin should not be tied to the POR pin.
7.4.2 Hard Reset
A hard reset will reset everything on the device except the PLLs, test, emulation logic, and reset-isolated modules.
POR should also remain de-asserted during this time.
Hard reset is initiated by the following:
•
RESET pin
•
RSCTRL Register in PLLCTL
•
Watchdog timer
•
Emulation
All the above initiators, by default, are configured to act as hard reset. Except emulation, all of the other 3 initiators
can be configured as soft resets in the RSCFG Register in PLLCTL.
The following sequence must be followed during a hard reset:
1.
The RESET pin is pulled active low for a minimum of 24 CLKIN1 cycles. During this time the RESET signal is
able to propagate to all modules (except those specifically mentioned above). All I/O are Hi-Z for modules
affected by RESET, to prevent off-chip contention during the warm reset.
2.
Once all logic is reset, RESETSTAT is driven active to denote that the device is in reset.
3.
The RESET pin can now be released. A minimal device initialization begins to occur. Note that configuration
pins are not re-latched and clocking is unaffected within the device.
4.
After device initialization is complete, the RESETSTAT pin is de-asserted (driven high).
Note—
The POR pin should be held inactive (high) throughout the warm reset sequence. Otherwise, if POR
is activated (brought low), the minimum POR pulse width must be met. The RESET pin should not be tied
to the POR pin.
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