Over operating temperature range unless otherwise noted. Pins: LPWRB, INT_DR, OUT0, OUT1, OUT2, OUT3, and ADDR.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
OH
Output high voltage, OUTx pins
I
SOURCE
= 400 µA
0.8 × V
DD
V
V
OL
Output low voltage, OUTx pins
I
SINK
= 400 µA
0.2 × V
DD
V
I
L
Digital input leakage current
–500
500
nA
V
OL_INTB
Output low voltage, INTB pin
3 mA sink current
0.4
V
6.7 I
2
C Interface
MIN
TYP
MAX
UNIT
VOLTAGE LEVELS
V
IH_I2C
Input high voltage
0.7 × V
DD
V
V
IL_I2C
Input low voltage
0.3 × V
DD
V
V
OL_I2C
Output low voltage
3 mA sink current
0.2 × V
DD
V
HYS
I2C
Hysteresis
0.05 × V
DD
V
I
2
C TIMING CHARACTERISTICS
f
SCL
Clock frequency
400
kHz
t
LOW
Clock low time
1.3
µs
t
HIGH
Clock high time
0.6
µs
t
HD;STA
Hold time repeated START condition
After this period, the first
clock pulse is generated.
0.6
µs
t
SU;STA
Set-up time for a repeated START
condition
0.6
µs
t
HD;DAT
Data hold time
0
µs
t
SU;DAT
Data set-up time
100
ns
t
SU;STO
Set-up time for STOP condition
0.6
µs
t
BUF
Bus free time between a STOP and
START condition
1.3
µs
t
VD;DAT
Data valid time
0.9
µs
t
VD;ACK
Data valid acknowledge time
0.9
µs
t
SP
Pulse width of spikes that must be
suppressed by the input filter
50
ns
(1)
This parameter is specified by design and/or characterization and is not tested in production.
6.8 Timing Diagram
SCL
SDA
t
HD;STA
t
LOW
t
r
t
HD;DAT
t
HIGH
t
f
t
SU;DAT
t
SU;STA
t
SU;STO
t
f
START
REPEATED
START
STOP
t
HD;STA
START
t
SP
t
r
t
BUF
Figure 6-1. I
2
C Timing Diagram
SNOSDD0 – DECEMBER 2021
6
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