Table 7-3. STATUS Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
0
REGISTER_FLAG
R
0h
Register Integrity Flag
Reports if any register's value has an unexpected change. Cleared
by a read of the status register.
0h = No unexpected register change
1h = Unexpected register change
7.5.1.2 OUT Register (Offset = 1h) [Reset = 00h]
OUT Register Field Descriptions
.
Return to the
Channel output logic states
Table 7-4. OUT Register Field Descriptions
Bit
Field
Type
Reset
Description
7-5
RESERVED
R
0h
Reserved
4
DATA_RDY
R
0h
Output Logic State for pre-processed data capture for any enabled
channel. Bit cleared on read.
0h = Data Capture in progress
1h = New Data available
3
OUT3
R
0h
Button output output Logic State for Channel 3
0h = No button press detected on Channel 3
1h = Button press detected on Channel 3
2
OUT2
R
0h
Button output Logic State for Channel 2
0h = No button press detected on Channel 2
1h = Button press detected on Channel 2
1
OUT1
R
0h
Button output Logic State for Channel 1
0h = No button press detected on Channel 1
1h = Button press detected on Channel 1
0
OUT0
R
0h
Button output Logic State for Channel 0
0h = No button press detected on Channel 0
1h = Button press detected on Channel 0.
7.5.1.3 DATA0_LSB Register (Offset = 2h) [Reset = 00h]
DATA0_LSB Register Field Descriptions
Return to the
The lower 8 bits of the Button 0 data (Two's complement
Table 7-5. DATA0_LSB Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
DATA0[7:0]
R
0h
The lower 8 bits of Channel 0 button data (Two's complement).
7.5.1.4 DATA0_MSB Register (Offset = 3h) [Reset = 00h]
DATA0_MSB is shown in
DATA0_MSB Register Field Descriptions
Return to the
The upper 4 bits of the Button 0 data (Two's complement)
SNOSDD0 – DECEMBER 2021
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