GND
JTAG /
DEBUG
P50_GPIO_00
P55_GPIO_01
P57_GPIO_02
P58_GPIO_03
P59_GPIO_04
P60_GPIO_05
P61_GPIO_06
P62_GPIO_07
P63_GPIO_08
P64_GPIO_09
P01_GPIO_10
P02_GPIO_11
P03_GPIO_12
P04_GPIO_13
P07_GPIO_16
P08_GPIO_17
P15_GPIO_22
P18_GPIO_28
P53_GPIO_30
P05_GPIO_14
P06_GPIO_15
P30_GPIO_27
P29_GPIO_26
EXTERNAL
PROGRAMMING
SFL_CLK
SFL_MOSI
SFL_MISO
SFL_nCS
1
2
3
4
5
6
J1
VCC
GND
1pF
C2
3.3nH
L1
GND
GND
1
2
E1
JTAG_TDI
JTAG_TCK
JTAG_TMS
JTAG_TDO
VCC
GND
GND
100µF
C6
100µF
C7
Optional:
Consider adding extra decoupling
capacitors if the battery cannot source
the peak cu rrents.
VCC
0.1µF
C3
0.1µF
C4
GND
GND
SOP[2:0] USED FOR
FACTORY RESTORE
Matching circuit shown below is for
the antenna. The module is matched
internally to 50
. Final solution
Ω
may require antenna matching
optimization with a pi-network
270
R1
SEE TABLE 4-1 FOR
VBAT_RESET and nRESET
CONNECTION OPTIONS
GND
1
GND
2
GPIO_10
3
GPIO_11
4
GPIO_14
5
GPIO_15
6
GPIO_16
7
GPIO_17
8
GPIO_12
9
GPIO_13
10
GPIO_22
11
JTAG_TDI
12
FLASH_SPI_MISO
13
FLASH_SPI_CS_IN
14
FLASH_SPI_CLK
15
GND
16
FLASH_SPI_MOSI
17
JTAG_TDO
18
GPIO_28
19
NC
20
JTAG_TCK
21
JTAG_TMS
22
SOP2
23
SOP1
24
GND
27
GND
28
NC
29
GND
30
RF_BG
31
GND
32
NC
33
SOP0
34
RESET
35
VBAT_RESET
36
VBAT1
37
GND
38
NC
39
VBAT2
40
NC
41
GPIO_30
42
GND
43
GPIO_0
44
NC
45
GPIO_01
46
GPIO_02
47
GPIO_03
48
GPIO_04
49
GPIO_05
50
GPIO_06
51
GPIO_07
52
GPIO_08
53
GPIO_09
54
GND
55
GND
56
GND
57
GND
58
GND
59
GND
60
GND
61
GND
62
GND
63
ANT_SEL1
25
ANT_SEL2
26
U7
CC3220MODSF12MOBR
At a minimum, pull thes pins out
to test points to aid in debug:
Pin 48: CC_
WL_RS232_TX
Pin 49: CC_WL_RS232_RX
Pin 50: CC_WL_UART_TX
Pin 52: CC_NPW_UART_TX
Copyright © 2017, Texas Instruments Incorporated
For the board files and BOM, see the
.
Figure 10-1. CC3220MODx Typical Application Schematic
SWRS206E – MARCH 2017 – REVISED MAY 2021
Copyright © 2021 Texas Instruments Incorporated
65
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