7.5 Drive Strength and Reset States for Analog-Digital Multiplexed Pins
describes the use, drive strength, and default state of analog- and digital-multiplexed pins at first-time
power up and reset (nRESET pulled low).
Table 7-4. Drive Strength and Reset States for Analog-Digital Multiplexed Pins
PIN
BOARD LEVEL
CONFIGURATION AND USE
DEFAULT STATE AT FIRST
POWER UP OR FORCED RESET
STATE AFTER CONFIGURATION
OF ANALOG SWITCHES (ACTIVE,
LPDS, and HIB POWER MODES)
MAXIMUM
EFFECTIVE
DRIVE
STRENGTH
(mA)
25
Connected to the enable pin of the
RF switch (ANT_SEL1). Other use
is not recommended.
Analog is isolated. The digital I/O
cell is also isolated.
Determined by the I/O state, as are
other digital I/Os.
4
26
Connected to the enable pin of the
RF switch (ANT_SEL2). Other use
is not recommended.
Analog is isolated. The digital I/O
cell is also isolated.
Determined by the I/O state, as are
other digital I/Os.
4
44
Generic I/O
Analog is isolated. The digital I/O
cell is also isolated.
Determined by the I/O state, as are
other digital I/Os.
4
42
Generic I/O
Analog is isolated. The digital I/O
cell is also isolated.
Determined by the I/O state, as are
other digital I/Os.
4
47
Analog signal (1.8-V absolute,
1.46-V full scale)
ADC is isolated. The digital I/O cell
is also isolated.
Determined by the I/O state, as are
other digital I/Os.
4
48
Analog signal (1.8-V absolute,
1.46-V full scale)
ADC is isolated. The digital I/O cell
is also isolated.
Determined by the I/O state, as are
other digital I/Os.
4
49
Analog signal (1.8-V absolute,
1.46-V full scale)
ADC is isolated. The digital I/O cell
is also isolated.
Determined by the I/O state, as are
other digital I/Os.
4
50
Analog signal (1.8-V absolute,
1.46-V full scale)
ADC is isolated. The digital I/O cell
is also isolated.
Determined by the I/O state, as are
other digital I/Os.
4
7.6 Pad State After Application of Power to Chip, but Before Reset Release
When a stable power is applied to the CC3220MODx or CC3220MODAx module for the first time or when supply
voltage is restored to the proper value following a prior period with supply voltage below 1.5 V, the level of
the digital pads are undefined in the period starting from the release of nRESET and until the DIG_DCDC of
the CC3220x chip powers up. This period is less than approximately 10 ms. During this period, pads can be
internally pulled weakly in either direction. If a certain set of pins are required to have a definite value during this
pre-reset period, an appropriate pullup or pulldown must be used at the board level. The recommended value of
these external pullup or pulldown resistors is 2.7 kΩ.
SWRS206E – MARCH 2017 – REVISED MAY 2021
26
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