Texas Instruments CC3120MOD, Руководство пользователя

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Table 8-11 lists the I
2
C timing parameters.
Table 8-11. I
2
C Timing Parameters
(3)
ITEM NAME DESCRIPTION MIN MAX UNIT
T2 t
LP
Clock low period See
(1)
System clock
T3 t
SRT
SCL/SDA rise time See
(2)
ns
T4 t
DH
Data hold time NA
T5 t
SFT
SCL/SDA fall time 3 ns
T6 t
HT
Clock high time See
(1)
System clock
T7 t
DS
Data setup time tLP/2 System clock
T8 t
SCSR
Start condition setup time 36 System clock
T9 t
SCS
Stop condition setup time 24 System clock
(1) This value depends on the value programmed in the clock period register of I
2
C. Maximum output frequency is the result of the minimal
value programmed in this register.
(2) Because I
2
C is an open-drain interface, the controller can drive logic 0 only. Logic is the result of external pullup. Rise time depends on
the value of the external signal capacitance and external pullup register.
(3) All timing is with 6-mA drive and 20-pF load.
8.14.5.5 IEEE 1149.1 JTAG
The Joint Test Action Group (JTAG) port is an IEEE standard that defines a test access port (TAP) and
boundary scan architecture for digital integrated circuits and provides a standardized serial interface to control
the associated test logic. For detailed information on the operation of the JTAG port and TAP controller, see the
IEEE Standard 1149.1,
Test Access Port and Boundary-Scan Architecture .
Figure 8-14 shows the JTAG timing diagram.
T2 T3
T4
T7 T8
T7 T8
T9 T10 T9 T10
T1 T11
TDI Input Valid
TDO Output Valid
TDO Output Valid
TMS Input Valid
TDI Input Valid
TCK
TMS
TDI
TDO
TMS Input Valid
Figure 8-14. JTAG Timing Diagram
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SWRS206E – MARCH 2017 – REVISED MAY 2021
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