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Texas Instruments ADS79 EVM-PDK Series, Руководство пользователя

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Texas Instruments ADS79 EVM-PDK Series Скачать руководство пользователя страница 48

MXO

AINP

Ch0

Chn 

Ch1

ADC

GPIO 0
GPIO 1

SDI

GPIO 2

SCLK
CS

SDO

REF

10  F

P

REF5025

o/p

See 

Note A

GPIO 3

150 pF 

150 pF 

R

SOURCE

R

SOURCE

150 pF 

R

SOURCE

To

Host

200 

7 pF

3 pF

20 M

3 pF

5 pF

80 

Ch0 assumed to be on
Chn assumed to be off

Ch0

Chn

MXO

AINP

48

ADS7950, ADS7951, ADS7952, ADS7953, ADS7954, ADS7955
ADS7956, ADS7957, ADS7958, ADS7959, ADS7960, ADS7961

SLAS605C – JUNE 2008 – REVISED JULY 2018

www.ti.com

Product Folder Links:

ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958

ADS7959 ADS7960 ADS7961

Submit Documentation Feedback

Copyright © 2008–2018, Texas Instruments Incorporated

Application Information (continued)

Figure 62. ADC and MUX Equivalent Circuit

9.2 Typical Applications

9.2.1 Unbuffered Multiplexer Output (MXO)

This application is the most typical application, but requires the lowest R

SOURCE

for good performance. In this

configuration, the 2xV

REF

range allows larger source impedance than the 1xV

REF

range because the 1xV

REF

range LSB size is smaller, thus making it more sensitive to settling error.

A.

A restriction on the source impedance exists. R

SOURCE

≤

100

Ω

for the 1xV

REF

12-bit settling at 1 MSPS or R

SOURCE

≤

250

Ω

for the 2xV

REF

12-bit settling at 1 MSPS.

Figure 63. Application Diagram for an Unbuffered MXO

9.2.1.1 Design Requirements

The design is optimized to show the input source impedance (R

SOURCE

) from the 100

Ω

to 10000

Ω

required to

meet the 1-LSB settling at 12-bit, 10-bit, and 8-bit resolutions at different throughput in 1xV

REF

(2.5-V) and

2xV

REF

(5-V) input ranges.

9.2.1.2 Detailed Design Procedure

Although the required input source impedance can be estimated assuming a 0.5-V initial error and exponential
recovery during sampling (acquisition) time, this estimation over-simplifies the complex interaction between the
converter and source, thus yielding inaccurate estimates. Thus, this design uses an iterative approach with the
converter itself to provide reliable impedance values.

To determine the actual maximum source impedance for a particular resolution and sampling rate, two
subsequent channels are set at least 95% of the full-scale range apart. With a 1xV

REF

range and 2.5 V

REF

, the

channel difference is at least 2.375 V. With 2xV

REF

and 2.5 V

REF

, the difference is at least 4.75 V. With a source

impedance from 100

Ω

to 10,000

Ω

, the conversion runs at a constant rate and a channel update is issued that

captures the first couple samples after the update. This process is repeated at least 100 times to remove any
noise and to show a clear settling error. The first sample after the channel update is then compared against the
second one. If the first and second samples are more than 1 LSB apart, throughput rate is reduced until the
settling error becomes 1 LSB, which then sets the maximum throughput for the selected impedance. The whole
process is repeated for nine different impedances from 100

Ω

to 10000

Ω

.

Содержание ADS79 EVM-PDK Series

Страница 1: ...gram 3 Description The ADS79xx is a 12 10 8 bit pin compatible multichannel analog to digital converter family The device comparison table shows all twelve devices from this product family The devices include a capacitor based SAR A D converter with inherent sample and hold The devices accept a wide analog supply range from 2 7 V to 5 25 V Very low power consumption makes these devices suitable fo...

Страница 2: ...Mechanical Packaging and Orderable Information 55 4 Revision History NOTE Page numbers for previous revisions may differ from page numbers in the current version Changes from Revision B July 2015 to Revision C Page Changed 0 to 2 5 V and 0 to 5 V to 0 to VREF and 0 to 2 x VREF in Input Range Features bullet 1 Changed GPIO Features bullet 1 Changed Optical Line Card Monitoring and Multi Channel Gen...

Страница 3: ...54 55 56 57 table 41 Changed 10 Bit to 8 Bit in title of Ideal Input Voltages for 8 Bit Devices and Digital Output Codes for 8 Bit Devices ADS7958 59 60 61 table 42 Changed Application Diagram for an Unbuffered MXO figure note 48 Changed Recommended Layout figure title to Recommended Layout for the TSSOP Packaged Device 52 Added Recommended Layout for the VQFN Packaged Device figure 53 Changes fro...

Страница 4: ...full scale input span range 2 test conditions 15 Added while 2VREF VA to full scale input span range 2 test conditions 15 Changed Vref reference voltage at REFP min value from 2 49 V to 2 0 V 16 Changed Vref reference voltage at REFP max value from 2 51 V to 3 0 V 16 Changed tsu1 values from max to min 17 Changed tsu2 values from max to min 17 Added TOTAL UNADJUSTED ERROR TUE Max graph 25 Added TO...

Страница 5: ...10 11 12 13 14 15 38 37 36 35 34 33 32 30 29 28 27 26 25 24 31 GPIO2 GPIO3 REFM REFP VA AGND MXO AINP AINM AGND CH15 CH14 CH13 CH12 CH11 GPIO1 GPIO0 VBD BDGND SDO SDI SCLK CS AGND VA CH0 CH1 CH2 CH3 CH4 ADS7953 ADS7957 ADS7961 16 17 18 19 CH10 CH9 CH8 AGND 23 22 21 20 CH5 CH6 CH7 AGND 1 8 9 16 32 25 24 17 AGND AINM AINP MXO CH15 CH12 CH13 CH14 SCLK VA AGND CS CH0 CH3 CH2 CH1 CH11 CH10 CH9 CH8 CH7 ...

Страница 6: ...ESCRIPTION NAME ADS7953 ADS7957 ADS7961 ADS7952 ADS7956 ADS7960 ADS7951 ADS7955 ADS7959 ADS7950 ADS7954 ADS7958 REFERENCE REFP 4 4 4 4 Analog input Reference input REFM 3 3 3 3 Analog input Reference ground ADC ANALOG INPUT AINP 8 8 8 8 Analog input ADC input signal AINM 9 9 9 9 Analog input ADC input ground MULTIPLEXER MXO 7 7 7 7 Analog output Multiplexer output Ch0 28 28 20 20 Analog input Anal...

Страница 7: ...ROL SIGNALS CS 31 31 23 23 Digital input Chip select input pin active low SCLK 32 32 24 24 Digital input Serial clock input pin SDI 33 33 25 25 Digital input Serial data input pin SDO 34 34 26 26 Digital output Serial data output pin GENERAL PURPOSE INPUTS OUTPUTS 1 GPIO0 37 37 29 29 Digital I O General purpose input or output Alarm Digital output Active high alarm output For configuration see the...

Страница 8: ...nput channel for multiplexer Ch2 18 16 11 9 Analog input Analog input channel for multiplexer Ch3 17 15 10 8 Analog input Analog input channel for multiplexer Ch4 16 14 9 Analog input Analog input channel for multiplexer Ch5 15 13 8 Analog input Analog input channel for multiplexer Ch6 14 12 7 Analog input Analog input channel for multiplexer Ch7 13 11 6 Analog input Analog input channel for multi...

Страница 9: ...DS7951 ADS7955 ADS7959 ADS7950 ADS7954 ADS7958 1 This pin has programmable dual functionality See Table 12 for functionality programming SDO 26 26 19 19 Digital output Serial data output pin GENERAL PURPOSE INPUT OUTPUT 1 GPIO0 29 29 22 22 Digital I O General purpose input or output Alarm Digital output Active high alarm output For configuration see the Programming section POWER SUPPLY AND GROUND ...

Страница 10: ...ations 7 Specifications 7 1 Absolute Maximum Ratings over operating free air temperature range unless otherwise noted 1 2 MIN MAX UNIT AINP or CHn to AGND 0 3 VA 0 3 V VA to AGND VBD to BDGND 0 3 7 V Digital input voltage to BDGND 0 3 7 V Digital output to BDGND 0 3 VA 0 3 V Input current to any pin except supply pins 10 10 mA Operating temperature 40 125 C Junction temperature TJ Max 150 C Storag...

Страница 11: ... resistance 29 8 22 9 C W RθJB Junction to board thermal resistance 44 7 43 1 C W ψJT Junction to top characterization parameter 2 9 0 8 C W ψJB Junction to board characterization parameter 44 1 42 5 C W RθJC bot Junction to case bottom thermal resistance n a n a C W 1 For more information about traditional and new thermal metrics see the Semiconductor and IC Package Thermal Metrics application re...

Страница 12: ...C to 125 C fsample 1 MHz unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG INPUT Full scale input span 1 Range 1 0 VREF V Range 2 while 2xVREF VA 0 2 VREF Absolute input range Range 1 0 2 VREF 0 2 V Range 2 while 2xVREF VA 0 2 2 VREF 0 2 Input capacitance 15 pF Input leakage current TA 125 C 61 nA SYSTEM PERFORMANCE Resolution 12 Bits No missing codes ADS795XSB 2 12 Bits ADS...

Страница 13: ... 71 3 dB 100 kHz ADS795XS 2 68 71 3 Spurious free dynamic range 100 kHz 84 dB Small signal bandwidth At 3 dB 47 MHz Channel to channel crosstalk Any off channel with 100 kHz Full scale input to channel being sampled with DC input isolation crosstalk 95 dB From previously sampled to channel with 100 kHz Full scale input to channel being sampled with DC input memory crosstalk 85 EXTERNAL REFERENCE I...

Страница 14: ... 0 20 2 VREF 0 20 Input capacitance 15 pF Input leakage current TA 125 C 61 nA SYSTEM PERFORMANCE Resolution 10 Bits No missing codes 10 Bits Integral linearity 0 5 0 2 0 5 LSB 2 Differential linearity 0 5 0 2 0 5 LSB Offset error 3 1 5 0 5 1 5 LSB Gain error Range 1 1 0 1 1 LSB Range 2 0 1 SAMPLING DYNAMICS Conversion time 20 MHz SCLK 800 ns Acquisition time 325 ns Maximum throughput rate 20 MHz ...

Страница 15: ...hroughput 1 8 mA At VA 2 7 to 3 6 V static state 1 05 1 At VA 4 7 to 5 25 V and 1 MHz throughput 2 3 3 At VA 4 7 to 5 25 V static state 1 1 1 5 Power down state supply current 1 μA VBD supply current VA 5 25V fs 1MHz 1 mA Power up time 1 μs Invalid conversions after power up or reset 1 Conversion 1 Ideal input span does not include gain or offset error 2 LSB means least significant bit 3 Measured ...

Страница 16: ...stortion 100 kHz 49 Spurious free dynamic range 100 kHz 78 dB Full power bandwidth At 3 dB 47 MHz Channel to channel crosstalk Any off channel with 100 kHz Full scale input to channel being sampled with DC input 95 dB From previously sampled to channel with 100 kHz Full scale input to channel being sampled with DC input 85 EXTERNAL REFERENCE INPUT VREF reference voltage at REFP 2 2 5 3 V Reference...

Страница 17: ...to start of next conversion VBD 1 8 V 40 ns VBD 3 V 40 VBD 5 V 40 td1 Delay time CS low to first data DO 15 out VBD 1 8 V 38 ns VBD 3 V 27 VBD 5 V 17 tsu1 Setup time CS low to first rising edge of SCLK VBD 1 8 V 8 ns VBD 3 V 6 VBD 5 V 4 td2 Delay time SCLK falling to SDO next data bit valid VBD 1 8 V 35 ns VBD 3 V 27 VBD 5 V 17 th1 Hold time SCLK falling to SDO data bit valid VBD 1 8 V 7 ns VBD 3 ...

Страница 18: ...tten through SDI in Frame n 1 GPI status is latched in on CS falling edge and transferred to SDO frame n Top 4 Bit Top 4 Bit Frame n 1 Frame n Analog I P Settling After Chan Change Acquisition Phase tacq Conversion Phase Conversion Phase tcnv 18 ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 SLAS605C JUNE 2008 REVISED JULY 2018 www ti com Product Fo...

Страница 19: ... td3 tsu1 td1 th1 tsu2 td2 th2 DI 13 1 t Throughput Single Frame tq tw1 19 ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 www ti com SLAS605C JUNE 2008 REVISED JULY 2018 Product Folder Links ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 Submit Documentation Feedback Copyright 2008 2018 Texas Instrume...

Страница 20: ...0 9 1 1 1 1 2 1 3 1 4 1 5 2 7 3 4 4 1 4 8 5 5 VA Supply Current mA VA Supply Voltage V T 25 C A 20 ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 SLAS605C JUNE 2008 REVISED JULY 2018 www ti com Product Folder Links ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 Submit Documentation Feedback Copyright ...

Страница 21: ... 2 0 4 0 6 0 8 1 2 7 3 2 3 7 4 2 4 7 5 2 DNL Differential Nonlinearity LSBs DNL max DNL min 5 5 VA Supply Voltage V f 1 MSPS T 25 C S A 21 ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 www ti com SLAS605C JUNE 2008 REVISED JULY 2018 Product Folder Links ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 ...

Страница 22: ... 0 0 2 0 4 0 6 0 8 1 2 7 3 4 4 1 4 8 5 5 Gain Error LSBs VA Supply Voltage V VBD 1 8 V f 1 MSPS T 25 C S A 22 ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 SLAS605C JUNE 2008 REVISED JULY 2018 www ti com Product Folder Links ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 Submit Documentation Feedback...

Страница 23: ... 1 4 8 5 5 SFDR Spurious Free Dynamic Range dB VA Supply Voltage V VBD 3 V f 1 MSPS f 100 kHz T 25 C S IN A 23 ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 www ti com SLAS605C JUNE 2008 REVISED JULY 2018 Product Folder Links ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 Submit Documentation Feedbac...

Страница 24: ...69 69 5 70 70 5 71 71 5 72 72 5 73 10 30 50 70 90 110 130 150 f Input Frequency KHz IN SINAD Signal to Noise and Distortion dB VA 5 V VBD 3 V f 1 MSPS T 25 C MXO Shorted to AINP S A 24 ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 SLAS605C JUNE 2008 REVISED JULY 2018 www ti com Product Folder Links ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 AD...

Страница 25: ... DNL min DNL Differential Nonlinearity LSBs VA 5 V VBD 5 V f 1 MSPS S 25 ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 www ti com SLAS605C JUNE 2008 REVISED JULY 2018 Product Folder Links ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 Submit Documentation Feedback Copyright 2008 2018 Texas Instrument...

Страница 26: ...on dB VA 5 V VBD 5 V f 1 MSPS S 26 ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 SLAS605C JUNE 2008 REVISED JULY 2018 www ti com Product Folder Links ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 Submit Documentation Feedback Copyright 2008 2018 Texas Instruments Incorporated Typical Characteristics...

Страница 27: ...INL LSBs INL VA 5 V VBD 5 V f 1 MSPS S 27 ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 www ti com SLAS605C JUNE 2008 REVISED JULY 2018 Product Folder Links ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 Submit Documentation Feedback Copyright 2008 2018 Texas Instruments Incorporated 7 12 Typical Cha...

Страница 28: ...hese four pins can be individually programmed as GPO or GPI It is also possible to use them for preassigned functions refer to Table 11 GPO data can be written into the device through the SDI line The device refreshes the GPO data on the CS falling edge as per the SDI data written in previous frame Similarly the device latches GPI status on the CS falling edge and outputs the GPI data on the SDO l...

Страница 29: ... It can be powered down by writing DI05 1 in the Mode Control register refer to Table 1 Table 2 and Table 5 in this case the device powers down on the 16th falling edge of SCLK in the next data frame Another way to powerdown the device is through GPIO GPIO3 can act as a PD input refer to Table 11 for assigning this functionality to GPIO3 This is an asynchronous and active low input The device powe...

Страница 30: ...ascending order 8 4 2 Device Programming and Mode Control The following section describes device programming and mode control These devices feature two types of registers to configure and operate the devices in different modes These registers are referred as Configuration Registers There are two types of Configuration Registers namely Mode Control Registers and Program Registers 8 4 2 1 Mode Contr...

Страница 31: ...d Device Functional Modes continued 1 The device continues its operation in manual mode channel 0 throughout the programming sequence and outputs valid conversion results It is possible to change channel range GPIO by inserting extra frames in between two programming blocks It is also possible to bypass any programming block if the user does not intend to use that feature 2 It is possible to repro...

Страница 32: ...or channel to be selected DI5 0 No power down DI4 0 as per GPIO settings SDO DO15 0 address or GPIO data conversion data of channel selected in frame n GPIO O P latched on CS falling edge as per DI 3 0 written in frame n I P Input status latched on falling edge of CS and transferred serially on SDO in the same frame CS Frame n 1 Entry into Manual Mode Sample Samples and converts channel selected i...

Страница 33: ...ows the same steps and the ADC sends the conversion data for CH7 and CH9 in the subsequent two frames Figure 51 Example Manual Mode Timing Diagram Table 1 Mode Control Register Settings for Manual Mode BITS RESET STATE LOGIC STATE FUNCTION DI15 12 0001 0001 Selects Manual Mode DI11 0 1 Enables programming of bits DI06 00 0 Device retains values of DI06 00 from the previous frame DI10 07 0000 This ...

Страница 34: ... 0 as per GPIO settings SDO DO15 0 address or GPIO data conversion data of channel selected in frame n GPIO O P latched on CS falling edge as per DI3 0 written in frame n I P Input status latched on falling edge of CS and transferred serially on SDO in the same frame CS Frame n 1 Entry into Auto 1 Mode Sample Samples and converts channel selected in frame n 1 ie Lowest channel in Auto 1 sequence M...

Страница 35: ... 53 before entering into this auto sequencing mode The device enters into Auto 1 mode on receiving the Auto 1 mode command in the Nth frame This step causes the device to find the first enabled channel in ascending order and switch the MUX for CH2 in the N 1 th frame In the N 2 th frame the ADC samples the signal on CH2 shifts out the conversion results and the MUX also internally switches to CH5 ...

Страница 36: ...st programmed channel in the Auto 1 Program Register 0 The channel counter increments every conversion No reset DI09 07 000 xxx Do not care DI06 0 0 Selects 0 to VREF input range Range 1 1 Selects 0 to 2xVREF input range Range 2 DI05 0 0 Device normal operation no powerdown 1 Device powers down on the 16th SCLK falling edge DI04 0 0 SDO outputs current channel address of the channel on DO15 12 fol...

Страница 37: ...wever it is not possible to change the range or write GPIO data into the device during programming Figure 54 Auto 1 Register Programming Flowchart Table 3 Program Register Settings for Auto 1 Mode BITS RESET STATE LOGIC STATE FUNCTION FRAME 1 DI15 12 NA 1000 Device enters Auto 1 program sequence Device programming is done in the next frame DI11 00 NA Do not care FRAME 2 DI15 00 All 1s 1 individual...

Страница 38: ...5 0 No power down DI4 0 as per GPIO settings SDO DO15 0 address or GPIO data conversion data of channel selected in frame n GPIO O P latched on CS falling edge as per DI3 0 written in frame n I P Input status latched on falling edge of CS and transferred serially on SDO in the same frame CS Frame n 1 Entry into Auto 2 Mode Sample Samples and converts channel 0 Mux Selects next higher channel in Au...

Страница 39: ...ascending order by programming the Auto 2 register as described in Figure 56 The device enters Auto 2 mode on receiving the Auto 2 mode command in the Nth frame This step causes the MUX to switch to CH0 in the N 1 th frame In the N 2 th frame the ADC samples and shifts out the conversion results for CH0 because the MUX internally switches to CH1 In the N 3 th frame the ADC samples and the shifts o...

Страница 40: ... i p range Range 2 DI05 0 0 Device normal operation no powerdown 1 Device powers down on the 16th SCLK falling edge DI04 0 0 SDO outputs the current channel address of the channel on DO15 12 followed by the 12 bit conversion result on DO11 00 1 GPIO3 GPIO0 data both input and output is mapped onto DO15 DO12 in the order shown below Lower data bits DO11 DO00 represent the 12 bit conversion result o...

Страница 41: ...mally whereas in the Manual mode it continues with the last selected channel The device ignores data on DI11 DI00 and continues operating as per the previous settings This feature is provided so that SDI can be held low when no changes are required in the Mode Control Register settings DI11 00 All 0 Device ignores these bits when DI15 12 is set to 0000 logic state 8 5 Programming 8 5 1 Digital Out...

Страница 42: ...ers NOTE GPIO 0 1 2 and 3 are available in the TSSOP packages Only GPIO 0 is available in the VQFN packages The device has four general purpose input and output GPIO pins Each of the four pins can be independently programmed as general purpose output GPO or general purpose input GPI It is also possible to use the GPIOs for some pre assigned functions refer to Table 11 for details GPO data can be w...

Страница 43: ...ng not allowed for QFN packaged devices DI02 0 1 GPIO2 pin is configured as general purpose output Program 1 for QFN packaged devices 0 GPIO2 pin is configured as general purpose input Setting not allowed for QFN packaged devices DI01 0 1 GPIO1 pin is configured as general purpose output Program 1 for QFN packaged devices 0 GPIO1 pin is configured as general purpose input Setting not allowed for Q...

Страница 44: ...s DI12 1 44 ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 SLAS605C JUNE 2008 REVISED JULY 2018 www ti com Product Folder Links ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 Submit Documentation Feedback Copyright 2008 2018 Texas Instruments Incorporated NOTE The device continues its operation in sel...

Страница 45: ...bits of the channel number in binary format The device programs the alarm for the channel represented by the binary number bbcc bb is programmed in the first frame DI13 NA 1 High alarm register selection 0 Low alarm register selection DI12 NA 0 Continue alarm programming sequence in next frame 1 Exit Alarm Programming in the next frame Note If the alarm programming sequence is not terminated using...

Страница 46: ...V to prevent source current saturation or slewing that causes significantly long settling times Fortunately significantly reducing disturbance error is easy to accomplish by simply placing a large enough capacitor at the input of each channel Specifically with a 150 pF capacitor instantaneous charge distribution keeps disturbance error less than 0 46 V because the internal input capacitance can on...

Страница 47: ... the device has respectable performance with up to 1kΩ source impedance This topology including a common ADC driver is useful when all channel signals are within the acceptable range of the ADC In this case the user can save on signal conditioning circuit for each channel Figure 61 Typical Application Diagram Showing Common Buffer PGA for All Channels When the converter samples an input the voltag...

Страница 48: ...SOURCE from the 100 Ω to 10000 Ω required to meet the 1 LSB settling at 12 bit 10 bit and 8 bit resolutions at different throughput in 1xVREF 2 5 V and 2xVREF 5 V input ranges 9 2 1 2 Detailed Design Procedure Although the required input source impedance can be estimated assuming a 0 5 V initial error and exponential recovery during sampling acquisition time this estimation over simplifies the com...

Страница 49: ...8 ADS7959 ADS7960 ADS7961 www ti com SLAS605C JUNE 2008 REVISED JULY 2018 Product Folder Links ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 Submit Documentation Feedback Copyright 2008 2018 Texas Instruments Incorporated Typical Applications continued 9 2 1 3 Application Curves These curves show the RSOURCE for an unbuffered MXO Figure 64 2xVREF I...

Страница 50: ... the input source impedance RSOURCE from the 100 Ω to 10000 Ω required to meet a 1 LSB settling at 12 bit 10 bit and 8 bit resolutions at different throughput in 1xVREF 2 5 V and 2xVREF 5 V input ranges 9 2 2 2 Detailed Design Procedure The design procedure is similar to the unbuffered MXO application but includes an operation amplifier in unity gain as a buffer The most important parameter for mu...

Страница 51: ...ck Copyright 2008 2018 Texas Instruments Incorporated Typical Applications continued 9 2 2 3 Application Curves These curves show the RSOURCE for an OPA192 buffered MXO Figure 67 2xVREF Input Range Settling with an OPA192 MXO Buffer Figure 68 1xVREF Input Range Settling with an OPA192 MXO Buffer 10 Power Supply Recommendations The devices are designed to operate from an analog supply voltage VA ra...

Страница 52: ... of the three supply pins as shown in Figure 69 and Figure 70 To minimize ground inductance ensure that each capacitor ground pin is connected to a grounding via by a very short and thick trace The REFP pin requires a 10 μF ceramic capacitor to meet performance specifications Place the capacitor directly next to the device This capacitor ground pin must be routed to the REFM pin by a very short tr...

Страница 53: ... AGND 53 ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 www ti com SLAS605C JUNE 2008 REVISED JULY 2018 Product Folder Links ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 Submit Documentation Feedback Copyright 2008 2018 Texas Instruments Incorporated Layout Examples continued Figure 70 Recommended L...

Страница 54: ...Click here Click here ADS7956 Click here Click here Click here Click here Click here ADS7957 Click here Click here Click here Click here Click here ADS7958 Click here Click here Click here Click here Click here ADS7959 Click here Click here Click here Click here Click here ADS7960 Click here Click here Click here Click here Click here ADS7961 Click here Click here Click here Click here Click here ...

Страница 55: ...ling and installation procedures can cause damage ESD damage can range from subtle performance degradation to complete device failure Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications 12 7 Glossary SLYZ022 TI Glossary This glossary lists and explains terms acronyms and definitions 13...

Страница 56: ...RoHS no Sb Br CU NIPDAU Level 2 260C 1 YEAR 40 to 125 ADS7950 ADS7950SRGER LIFEBUY VQFN RGE 24 3000 Green RoHS no Sb Br CU NIPDAU Level 3 260C 168 HR 40 to 125 ADS 7950 ADS7950SRGET LIFEBUY VQFN RGE 24 250 Green RoHS no Sb Br CU NIPDAU Level 3 260C 168 HR 40 to 125 ADS 7950 ADS7951SBDBT ACTIVE TSSOP DBT 30 60 Green RoHS no Sb Br CU NIPDAU Level 2 260C 1 YEAR 40 to 125 ADS7951 B ADS7951SBDBTR ACTIV...

Страница 57: ...DS7952SBRHBT ACTIVE VQFN RHB 32 250 Green RoHS no Sb Br CU NIPDAU Level 3 260C 168 HR 40 to 125 ADS 7952 B ADS7952SDBT ACTIVE TSSOP DBT 38 50 Green RoHS no Sb Br CU NIPDAU Level 2 260C 1 YEAR 40 to 125 ADS7952 ADS7952SDBTG4 ACTIVE TSSOP DBT 38 50 Green RoHS no Sb Br CU NIPDAU Level 2 260C 1 YEAR 40 to 125 ADS7952 ADS7952SDBTR ACTIVE TSSOP DBT 38 2000 Green RoHS no Sb Br CU NIPDAU Level 2 260C 1 YE...

Страница 58: ... ADS7954SRGET ACTIVE VQFN RGE 24 250 Green RoHS no Sb Br CU NIPDAU Level 3 260C 168 HR 40 to 125 ADS 7954 ADS7955SDBT ACTIVE TSSOP DBT 30 60 Green RoHS no Sb Br CU NIPDAU Level 2 260C 1 YEAR 40 to 125 ADS7955 ADS7955SDBTR ACTIVE TSSOP DBT 30 2000 Green RoHS no Sb Br CU NIPDAU Level 2 260C 1 YEAR 40 to 125 ADS7955 ADS7955SRGER ACTIVE VQFN RGE 24 3000 Green RoHS no Sb Br CU NIPDAU Level 3 260C 168 H...

Страница 59: ...7959SDBTR ACTIVE TSSOP DBT 30 2000 Green RoHS no Sb Br CU NIPDAU Level 2 260C 1 YEAR 40 to 125 ADS7959 ADS7959SRGER ACTIVE VQFN RGE 24 3000 Green RoHS no Sb Br CU NIPDAU Level 3 260C 168 HR 40 to 125 ADS 7959 ADS7959SRGET ACTIVE VQFN RGE 24 250 Green RoHS no Sb Br CU NIPDAU Level 3 260C 168 HR 40 to 125 ADS 7959 ADS7960SDBT ACTIVE TSSOP DBT 38 50 Green RoHS no Sb Br CU NIPDAU Level 2 260C 1 YEAR 4...

Страница 60: ...EC industry standard classifications and peak solder temperature 4 There may be additional marking which relates to the logo the lot trace code information or the environmental category on the device 5 Multiple Device Markings will be inside parentheses Only one Device Marking contained in parentheses and separated by a will appear on a device If a line is indented then it is a continuation of the...

Страница 61: ...PACKAGE OPTION ADDENDUM www ti com 18 Feb 2019 Addendum Page 6 NOTE Qualified Version Definitions Automotive Q100 devices qualified for high reliability automotive applications targeting zero defects ...

Страница 62: ... 8 3 1 6 8 0 16 0 Q1 ADS7951SBRGER VQFN RGE 24 3000 330 0 12 4 4 25 4 25 1 15 8 0 12 0 Q2 ADS7951SBRGET VQFN RGE 24 250 180 0 12 4 4 25 4 25 1 15 8 0 12 0 Q2 ADS7951SDBTR TSSOP DBT 30 2000 330 0 16 4 6 95 8 3 1 6 8 0 16 0 Q1 ADS7951SRGER VQFN RGE 24 3000 330 0 12 4 4 25 4 25 1 15 8 0 12 0 Q2 ADS7951SRGET VQFN RGE 24 250 180 0 12 4 4 25 4 25 1 15 8 0 12 0 Q2 ADS7952SBDBTR TSSOP DBT 38 2000 330 0 16...

Страница 63: ...S7956SRHBR VQFN RHB 32 3000 330 0 12 4 5 3 5 3 1 5 8 0 12 0 Q2 ADS7956SRHBT VQFN RHB 32 250 180 0 12 4 5 3 5 3 1 5 8 0 12 0 Q2 ADS7957SDBTR TSSOP DBT 38 2000 330 0 16 4 6 9 10 2 1 8 12 0 16 0 Q1 ADS7957SRHBR VQFN RHB 32 3000 330 0 12 4 5 3 5 3 1 5 8 0 12 0 Q2 ADS7957SRHBT VQFN RHB 32 250 180 0 12 4 5 3 5 3 1 5 8 0 12 0 Q2 ADS7958SDBTR TSSOP DBT 30 2000 330 0 16 4 6 95 8 3 1 6 8 0 16 0 Q1 ADS7958SR...

Страница 64: ...000 367 0 367 0 35 0 ADS7951SBRGET VQFN RGE 24 250 210 0 185 0 35 0 ADS7951SDBTR TSSOP DBT 30 2000 367 0 367 0 38 0 ADS7951SRGER VQFN RGE 24 3000 367 0 367 0 35 0 ADS7951SRGET VQFN RGE 24 250 210 0 185 0 35 0 ADS7952SBDBTR TSSOP DBT 38 2000 367 0 367 0 38 0 ADS7952SBRHBR VQFN RHB 32 3000 367 0 367 0 35 0 ADS7952SBRHBT VQFN RHB 32 250 210 0 185 0 35 0 ADS7952SDBTR TSSOP DBT 38 2000 367 0 367 0 38 0...

Страница 65: ... 0 35 0 ADS7956SRHBT VQFN RHB 32 250 210 0 185 0 35 0 ADS7957SDBTR TSSOP DBT 38 2000 367 0 367 0 38 0 ADS7957SRHBR VQFN RHB 32 3000 367 0 367 0 35 0 ADS7957SRHBT VQFN RHB 32 250 210 0 185 0 35 0 ADS7958SDBTR TSSOP DBT 30 2000 367 0 367 0 38 0 ADS7958SRGER VQFN RGE 24 3000 367 0 367 0 35 0 ADS7958SRGET VQFN RGE 24 250 210 0 185 0 35 0 ADS7959SDBTR TSSOP DBT 30 2000 367 0 367 0 38 0 ADS7959SRGER VQF...

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Страница 69: ...AGE VIEW Images above are just a representation of the package family actual package may vary Refer to the product data sheet for package details RGE 24 VQFN 1 mm max height PLASTIC QUAD FLATPACK NO LEAD 4204104 H ...

Страница 70: ...kage thermal pad must be soldered to the printed circuit board for thermal and mechanical performance PACKAGE OUTLINE www ti com 4219016 A 08 2017 VQFN 1 mm max height PLASTIC QUAD FLATPACK NO LEAD RGE0024H A 0 08 C 0 1 C A B 0 05 C B SYMM SYMM 4 1 3 9 4 1 3 9 PIN 1 INDEX AREA 1 MAX 0 05 0 00 SEATING PLANE C 2X 2 5 2X 2 5 20X 0 5 1 6 7 12 13 18 19 24 24X 0 30 0 18 24X 0 48 0 28 0 2 TYP PIN 1 ID OP...

Страница 71: ... on board fabrication site EXAMPLE BOARD LAYOUT 4219016 A 08 2017 www ti com VQFN 1 mm max height RGE0024H PLASTIC QUAD FLATPACK NO LEAD SYMM SYMM LAND PATTERN EXAMPLE SCALE 20X 2X 1 1 2X 1 1 3 825 3 825 2 7 1 6 7 12 13 18 19 24 25 24X 0 58 24X 0 24 20X 0 5 R0 05 TYP SOLDER MASK DETAILS NON SOLDER MASK DEFINED PREFERRED SOLDER MASK DEFINED 0 07 MAX ALL AROUND 0 07 MIN ALL AROUND METAL SOLDER MASK ...

Страница 72: ... recommendations EXAMPLE STENCIL DESIGN 4219016 A 08 2017 www ti com VQFN 1 mm max height RGE0024H PLASTIC QUAD FLATPACK NO LEAD SYMM SYMM SOLDER PASTE EXAMPLE BASED ON 0 125 mm THICK STENCIL EXPOSED PAD 78 PRINTED COVERAGE BY AREA SCALE 20X 3 825 3 825 0 694 TYP 0 694 TYP 4X 1 188 1 6 7 12 13 18 19 24 24X 0 24 24X 0 58 20X 0 5 R0 05 TYP METAL TYP 25 ...

Страница 73: ...VIEW Images above are just a representation of the package family actual package may vary Refer to the product data sheet for package details VQFN 1 mm max height RHB 32 PLASTIC QUAD FLATPACK NO LEAD 5 x 5 0 5 mm pitch 4224745 A ...

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Страница 77: ...se resources are subject to change without notice TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource Other reproduction and display of these resources is prohibited No license is granted to any other TI intellectual property right or to any third party intellectual property right TI disclaims responsibility for...

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