MXO
AINP
Ch0
Chn*
Ch2
Ch1
ADC
GPIO 0, H Alarm
GPIO 1, L Alarm
SDI
GPIO 2, Range
SCLK
CS
SDO
To
Host
REF
10 F
m
REF5025
o/p
From sensors, INA etc.
There is a restriction on
source impedance.
R
50
SOURCE
£
W
GPIO 3, PD
46
ADS7950, ADS7951, ADS7952, ADS7953, ADS7954, ADS7955
ADS7956, ADS7957, ADS7958, ADS7959, ADS7960, ADS7961
SLAS605C – JUNE 2008 – REVISED JULY 2018
Product Folder Links:
ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958
Copyright © 2008–2018, Texas Instruments Incorporated
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
In general applications, when the internal multiplexer is updated, the previously converted channel charge is
stored in the 15-pF internal input capacitance that disturbs the voltage at the newly selected channel. This
disturbance is expected to settle to 1 LSB during sampling (acquisition) time to avoid degrading converter
performance. The initial absolute disturbance error at the channel input must be less than 0.5 V to prevent
source current saturation or slewing that causes significantly long settling times. Fortunately, significantly
reducing disturbance error is easy to accomplish by simply placing a large enough capacitor at the input of each
channel. Specifically, with a 150-pF capacitor, instantaneous charge distribution keeps disturbance error less
than 0.46 V because the internal input capacitance can only hold up to 75 pC (or 5 V × 15 pF). The remaining
error must be corrected by the voltage source at each input, with impedance low enough to settle within 1 LSB.
The following application examples explain the considerations for the input source impedance (R
SOURCE
).
9.1.1 Analog Input
The ADS79xx device family offers 12/10/8-bit ADCSs with 16/12/8/4 channel multiplexers for analog input. The
multiplexer output is available on the MXO pin. AINP is the ADC input pin. The devices offers flexibility for a
system designer as both signals are accessible externally.
Typically it is convenient to short MXO to the AINP pin so that signal input to each multiplexer channel can be
processed independently. In this condition, TI recommends limiting source impedance to 50
Ω
or less. Higher
source impedance may affect the signal settling time after a multiplexer channel change. This condition can
affect linearity and total harmonic distortion.
GPIO 0,1,2 and 3 are available only in TSSOP packaged devices. QFN device offers 'GPIO 0' only. As a result all
references related to 'GPIO 0' only are valid in case of QFN package devices.
Figure 60. Typical Application Diagram Showing MXO Shorted to AINP
