MXO
AINP
Ch0
Chn*
Ch2
Ch1
ADC
High input
impedance PGA
(or non inverting buffer
such as THS4031)
GPIO1
2
3
GPIO
GPIO
PGA Gain
Control
GPIO0
high-alarm
low-alarm
SDI
SCLK
CS
SDO
To
Host
REF
10 µF
REF5025
o/p
See note A.
47
ADS7950, ADS7951, ADS7952, ADS7953, ADS7954, ADS7955
ADS7956, ADS7957, ADS7958, ADS7959, ADS7960, ADS7961
SLAS605C – JUNE 2008 – REVISED JULY 2018
Product Folder Links:
ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958
Copyright © 2008–2018, Texas Instruments Incorporated
Application Information (continued)
Another option is to add a common ADC driver buffer between the MXO and AINP pins. This relaxes the
restriction on source impedance to a large extent. Refer to
Typical Characteristics (All ADS79xx Family Devices)
for the effect of source impedance on device performance. The typical characteristics show that the device has
respectable performance with up to 1k
Ω
source impedance. This topology (including a common ADC driver) is
useful when all channel signals are within the acceptable range of the ADC. In this case the user can save on
signal conditioning circuit for each channel.
Figure 61. Typical Application Diagram Showing Common Buffer/PGA for All Channels
When the converter samples an input, the voltage difference between AINP and AGND is captured on the
internal capacitor array. The (peak) input current through the analog inputs depends upon a number of factors:
sample rate, input voltage, and source impedance. The current into the ADS79xx charges the internal capacitor
array during the sample period. After this capacitance has been fully charged, there is no further input current.
When the converter goes into hold mode, the input impedance is greater than 1 G
Ω
.
Care must be taken regarding the absolute analog input voltage. To maintain linearity of the converter, the Ch0 ..
Chn and AINP inputs should be within the limits specified. Outside of these ranges, converter linearity may not
meet specifications.
