Texas Instruments ADS54J54EVM, Руководство пользователя

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2.2.3 JESD204B Controls
Clicking on JESD204B Configuration opens the JESD204B Configuration controls tab, shown in Figure 4 .
Use the ADS54J54 data sheet ( SLASE67 ) for reference to assist with the descriptions of these various
controls. The ADS54J54 EVM SPI GUI comes with a number of configuration files that will set the EVM
into a known and tested configuration that works with the TSW14J56 capture card. Full control of the
JESD204B configuration is possible with the use of this tab of controls. Of primary importance are the
JESD204B parameters L, M, F, and K. The parameter M refers to the number of data converters in a
JESD204B link, and since the ADS54J54 is a four channel device, then M is assumed to be 4. The
parameter L refers to the number of lanes used. The ADS54J54 may use one lane per channel when in 2x
decimation mode to output 250 Msps or use 2 lanes per channel when outputting sample data at 500
Msps. L may then be either 4 or 8. The parameter F is the number of octets (an octet is half of a sample
transmitted per lane). The parameter K is a number of 'frames' of sample data bundled into a multiframe
of length K frames, and this sets the period of the SYSREF clock signal. The TSW14J56 capture card (or
other FPGA receiving JESD204B serial sample data from the EVM) must be configured with the same
parameters as the ADS54J54.
Figure 4. JESD204B Configuration Tab
8 ADS54J54 Evaluation Module SLAU616A – January 2015 – Revised January 2016
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