Software Control
2.2.4
LMK Controls
Click the
LMK04828
tab located in the top tab bar of the GUI. The bank of LMK04828 control tabs is
selected as shown in
. There are four lower level tabs for control of the LMK04828. The
LMK04828 is a dual-PLL clock device so there is a tab for setting controls for the first PLL and a tab for
setting controls of the second PLL. There is a tab for setting controls related to the programming of the
JESD204b SYSREF and SYNC signals. There is a tab for individual control of each of the 14 clock
outputs of the LMK04828. The first PLL is represented in the PLL1 Configuration tab. The first PLL
essentially takes a low-frequency reference and multiplies this up to an internal reference frequency. The
second PLL has a very clean narrow-bandwidth VCO of either 2.5 or 3.0 GHz that is locked to the internal
reference frequency from PLL1 and from this VCO the output clocks are generated.
Figure 5. LMK04828 PLL1 Configuration Tab
2.2.4.1
PLL1 Configuration
Much of this panel is organized in block diagram format to help visualize the function of the controls. The
function of PLL1 is to take an external reference clock, such as the 10-MHz reference from an oscillator
on the EVM, and generate a clean, low-jitter intermediate-frequency clock for use by the second PLL loop.
There are numerous integer divider values that may be used to create this intermediate frequency from
the external reference. This tab also contains the reset and power down controls for the whole LMK04828
device. Consult the LMK04828 data sheet (
) and design tools for more information regarding the
proper settings for configuring PLL1, particularly for the proper settings for the PLL1 phase detector and
charge pump values.
9
SLAU616A – January 2015 – Revised January 2016
ADS54J54 Evaluation Module
Copyright © 2015–2016, Texas Instruments Incorporated
