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2.2.4.2 PLL2 Configuration
Clicking PLL2 Configuration opens the PLL2 Configuration tab as shown in Figure 6 . Much of this panel is
organized in block diagram format to help visualize the function of the controls. In this tab there is the
control to select whether an external VCO is used or an internal VCO of frequency 2.5 GHz or 3.0 GHz.
Several integer divider ratios can be set to lock the VCO to the frequency from PLL1, labeled as OSCin.
After configuring PLL2 to select a VCO and locking it to the input reference resulting in the desired VCO
frequency, this VCO frequency is then used to generate 14 clock outputs which are normally used as 7
pairs of device clock and SYSREF system reference clocks. One of the device clock/SYSREF pairs is
connected to the FMC connector to source DCLK/SYSREF to the FPGA on the TSW14J56 capture card.
Another DCLK/SYSREF pair is used to clock the ADS54J54. The other 5 pairs of clocks are normally
powered down but may be configured as additional clock outputs. The block diagram at the bottom of the
PLL2 Configuration tab illustrates some of the operations that might be applied to the 7 DCLK/SYSREF
pairs, such as divider ratios or delay adjustments. The next two tabs provide the controls to select all
these available features that may be used to condition the DCLK/SYSREF pairs for a specific use. The
LMK04828 datasheet is indispensable in understanding the function of each of these many controls and
how these controls should be set for a specific use of the EVM.
Figure 6. LMK04828 PLL2 Configuration Tab
10 ADS54J54 Evaluation Module SLAU616A – January 2015 – Revised January 2016
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